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/openbmc/u-boot/board/armltd/vexpress/
H A Dvexpress_tc2.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/u-boot.h>
27 * bit 12 = Use per-cpu mailboxes for power management in armv7_boot_nonsec_default()
28 * bit 13 = Power down the non-boot cluster in armv7_boot_nonsec_default()
30 * It is only when both of these are false that U-Boot's current in armv7_boot_nonsec_default()
39 int ft_board_setup(void *fdt, bd_t *bd) in ft_board_setup() argument
43 const char *cci_compatible = "arm,cci-400-ctrl-if"; in ft_board_setup()
51 /* Booting in nonsec mode, disable CCI access */ in ft_board_setup()
52 offset = fdt_path_offset(fdt, "/cpus"); in ft_board_setup()
58 /* delete cci-control-port in each cpu node */ in ft_board_setup()
[all …]
/openbmc/u-boot/include/configs/
H A Dib62x0.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011-2012
16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
28 * mv-common.h should be defined after CMD configs since it used them
31 #include "mv-common.h"
50 "ubifsload 0x700000 ${fdt}; " \
52 "fdt addr 0x700000; fdt resize; fdt chosen; " \
53 "bootz 0x800000 - 0x700000"
60 "fdt=/boot/ib62x0.dtb\0" \
H A Dnsa310s.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
24 * mv-common.h should be defined after CMD configs since it used them
27 #include "mv-common.h"
42 "ubifsload 0x700000 ${fdt}; " \
44 "fdt addr 0x700000; fdt resize; fdt chosen; " \
45 "bootz 0x800000 - 0x700000"
52 "fdt=/boot/nsa310s.dtb\0" \
/openbmc/u-boot/drivers/usb/musb-new/
H A Domap2430.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2005-2007 by Texas Instruments
13 #include <dm/device-internal.h>
20 #include "linux-compat.h"
30 l = musb_readl(musb->mregs, OTG_FORCESTDBY); in omap2430_low_level_exit()
32 musb_writel(musb->mregs, OTG_FORCESTDBY, l); in omap2430_low_level_exit()
39 l = musb_readl(musb->mregs, OTG_FORCESTDBY); in omap2430_low_level_init()
40 l &= ~ENABLEFORCE; /* disable MSTANDBY */ in omap2430_low_level_init()
41 musb_writel(musb->mregs, OTG_FORCESTDBY, l); in omap2430_low_level_init()
52 (struct omap_musb_board_data *)musb->controller; in omap2430_musb_init()
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/openbmc/qemu/hw/arm/
H A Draspi4b.c6 * SPDX-License-Identifier: GPL-2.0-or-later
17 #include "qemu/error-report.h"
36 * (see https://datasheets.raspberrypi.com/bcm2711/bcm2711-peripherals.pdf
39 static int raspi_add_memory_node(void *fdt, hwaddr mem_base, hwaddr mem_len) in raspi_add_memory_node() argument
45 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", in raspi_add_memory_node()
47 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", in raspi_add_memory_node()
50 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); in raspi_add_memory_node()
51 ret = -1; in raspi_add_memory_node()
53 qemu_fdt_add_subnode(fdt, nodename); in raspi_add_memory_node()
54 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); in raspi_add_memory_node()
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H A Dimx8mp-evk.c6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "system/address-spaces.h"
12 #include "hw/arm/fsl-imx8mp.h"
14 #include "hw/qdev-properties.h"
16 #include "qemu/error-report.h"
20 static void imx8mp_evk_modify_dtb(const struct arm_boot_info *info, void *fdt) in imx8mp_evk_modify_dtb() argument
24 /* Temporarily disable following nodes until they are implemented */ in imx8mp_evk_modify_dtb()
26 "nxp,imx8mp-fspi", in imx8mp_evk_modify_dtb()
32 offset = fdt_node_offset_by_compatible(fdt, -1, dev_str); in imx8mp_evk_modify_dtb()
34 fdt_nop_node(fdt, offset); in imx8mp_evk_modify_dtb()
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H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/pci-bridge/pci_expander_bridge.h"
61 #include "hw/virtio/virtio-pci.h"
62 #include "hw/core/sysbus-fdt.h"
63 #include "hw/platform-bus.h"
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H A Dxlnx-zcu102.c20 #include "hw/arm/xlnx-zynqmp.h"
23 #include "qemu/error-report.h"
43 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
51 return s->secure; in OBJECT_DECLARE_SIMPLE_TYPE()
58 s->secure = value; in zcu102_set_secure()
65 return s->virt; in zcu102_get_virt()
72 s->virt = value; in zcu102_set_virt()
75 static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt) in zcu102_modify_dtb() argument
85 if (!s->secure) { in zcu102_modify_dtb()
86 node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware", in zcu102_modify_dtb()
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H A Dvexpress.c4 * Copyright (c) 2010 - 2011 B Labs Ltd.
20 * Contributions after 2012-01-13 are licensed under the terms of the
38 #include "qemu/error-report.h"
48 #include "target/arm/cpu-qom.h"
63 * the "legacy" one (used for A9) and the "Cortex-A Series"
189 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
190 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
218 unsigned int smp_cpus = ms->smp.cpus; in init_cpus()
233 if (object_property_find(cpuobj, "reset-cbar")) { in init_cpus()
234 object_property_set_int(cpuobj, "reset-cbar", periphbase, in init_cpus()
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/openbmc/openbmc/poky/meta/recipes-devtools/qemu/
H A Dqemu_10.0.0.bb5 DEPENDS += "glib-2.0 zlib pixman"
7 DEPENDS:append:libc-musl = " libucontext"
9 CFLAGS += "${@bb.utils.contains('DISTRO_FEATURES', 'x11', '', '-DEGL_NO_X11=1', d)}"
10 LDFLAGS:append:toolchain-clang:x86 = " -latomic"
12 RDEPENDS:${PN}-common:class-target += "bash"
14 EXTRA_OECONF:append:class-target = " --target-list=${@get_qemu_target_list(d)}"
15 EXTRA_OECONF:append:class-target:mipsarcho32 = "${@bb.utils.contains('BBEXTENDCURR', 'multilib', ' …
16 EXTRA_OECONF:append:class-nativesdk = " --target-list=${@get_qemu_target_list(d)}"
19 fdt sdl kvm pie slirp \
24 PACKAGECONFIG:class-nativesdk ??= "fdt sdl kvm pie slirp \
H A Dqemu.inc7 LICENSE = "GPL-2.0-only & LGPL-2.1-only"
9 DEPENDS += "bison-native meson-native ninja-native"
11 RDEPENDS:${PN}-ptest = "bash"
13 require qemu-targets.inc
14 # https://gitlab.com/qemu-project/qemu/-/commit/81e2b198a8cb4ee5fdf108bd438f44b193ee3a36 means
15 # we need a full python3-native setup
16 inherit pkgconfig ptest update-rc.d systemd python3native
21 SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
23 file://run-ptest \
24 file://fix-strerrorname_np.patch \
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/openbmc/u-boot/board/freescale/ls2080ardb/
H A Dls2080ardb.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <fsl-mc/fsl_mc.h>
46 if (gd->flags & GD_FLG_RELOC) in get_qixis_addr()
68 printf("Board: %s-RDB, ", buf); in checkboard()
196 return -1; in config_board_mux()
213 gd->env_addr = (ulong)&default_environment[0]; in board_init()
254 u32 svr = gur_in32(&gur->svr); in misc_init_r()
299 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); in detail_board_ddr_info()
302 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { in detail_board_ddr_info()
303 puts("\nDP-DDR "); in detail_board_ddr_info()
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/openbmc/qemu/
H A D.travis.yml5 - gcc
9 # - OS name (currently only linux)
10 # - OS distribution (e.g. "jammy" for Linux)
11 # - Names and values of visible environment variables set in .travis.yml or Settings panel
19 # $ travis encrypt -r "qemu/qemu" "irc.oftc.net#qemu"
23 …- secure: "F7GDRgjuOo5IUyRLqSkmDL7kvdU4UcH3Lm/W2db2JnDHTGCqgEdaYEYKciyCLZ57vOTsTsOgesN8iUT7hNHBd1K…
30 - SRC_DIR=".."
31 - BUILD_DIR="build"
32 - BASE_CONFIG="--disable-docs --disable-tools"
33 - TEST_BUILD_CMD=""
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/openbmc/qemu/tests/docker/dockerfiles/
H A Ddebian-tricore-cross.docker2 # Docker TriCore cross-compiler target
8 # Copyright (c) 2018 Philippe Mathieu-Daudé
10 # SPDX-License-Identifier: GPL-2.0-or-later
12 FROM docker.io/library/debian:11-slim
15 DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \
16 DEBIAN_FRONTEND=noninteractive eatmydata apt install -yy \
19 ca-certificates \
26 libglib2.0-dev \
27 libpixman-1-dev \
30 ninja-build \
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/openbmc/u-boot/board/freescale/ls1088a/
H A Dls1088a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
16 #include <fsl-mc/fsl_mc.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
137 regs_info->regs = ifc_cfg_qspi_nor_boot; in ifc_cfg_boot_info()
139 regs_info->regs = ifc_cfg_ifc_nor_boot; in ifc_cfg_boot_info()
141 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; in ifc_cfg_boot_info()
160 if (gd->flags & GD_FLG_RELOC) in get_qixis_addr()
196 int fixup_ls1088ardb_pb_banner(void *fdt) in fixup_ls1088ardb_pb_banner() argument
198 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); in fixup_ls1088ardb_pb_banner()
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/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
58 reg = readl(plat->regs + plat->ctl_reg); in socfpga_a10_clk_get_upstream()
[all …]
/openbmc/u-boot/board/freescale/lx2160a/
H A Deth_lx2160ardb.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <fsl-mc/fsl_mc.h>
19 #include <fsl-mc/ldpaa_wriop.h>
28 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); in get_inphi_phy_id()
31 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); in get_inphi_phy_id()
50 srds_s1 = in_le32(&gur->rcwsr[28]) & in board_eth_init()
161 gd->jt->strcpy = strcpy; in board_eth_init()
162 gd->jt->mdelay = mdelay; in board_eth_init()
163 gd->jt->mdio_get_current_dev = mdio_get_current_dev; in board_eth_init()
164 gd->jt->phy_find_by_mask = phy_find_by_mask; in board_eth_init()
[all …]
H A Dlx2160a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
18 #include <fsl-mc/fsl_mc.h>
125 /* Check RCW field sdhc1_base_pmux to enable/disable in esdhc_dspi_status_fixup()
128 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in esdhc_dspi_status_fixup()
144 /* Check RCW field sdhc2_base_pmux to enable/disable in esdhc_dspi_status_fixup()
147 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) in esdhc_dspi_status_fixup()
164 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in esdhc_dspi_status_fixup()
218 printf("Board: %s-QDS, ", buf); in checkboard()
220 printf("Board: %s-RDB, ", buf); in checkboard()
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/openbmc/u-boot/arch/sandbox/include/asm/
H A Du-boot-sandbox.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
30 * pci_map_physmem() - map a PCI device into memory
45 * @return 0 if OK, -ve on error
51 * pci_unmap_physmem() - undo a memory mapping
58 * @return 0 if OK, -ve on error
64 * sandbox_set_enable_pci_map() - Enable / disable PCI address mapping
67 * enable and disable this. It can be handled automatically by the emulator
73 * @enable: 0 to disable, 1 to enable
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/openbmc/qemu/.gitlab-ci.d/
H A Dcrossbuilds.yml2 - local: '/.gitlab-ci.d/crossbuild-template.yml'
4 cross-armhf-user:
7 job: armhf-debian-cross-container
9 IMAGE: debian-armhf-cross
11 cross-arm64-system:
14 job: arm64-debian-cross-container
16 IMAGE: debian-arm64-cross
18 cross-arm64-user:
21 job: arm64-debian-cross-container
23 IMAGE: debian-arm64-cross
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H A Dcrossbuild-template.yml7 - ccache
12 - source scripts/ci/gitlab-ci-section
13 - section_start setup "Pre-script setup"
14 - JOBS=$(expr $(nproc) + 1)
15 - cat /packages.txt
16 - section_end setup
18 - export CCACHE_BASEDIR="$(pwd)"
19 - export CCACHE_DIR="$CCACHE_BASEDIR/ccache"
20 - export CCACHE_MAXSIZE="500M"
21 - export PATH="$CCACHE_WRAPPERSDIR:$PATH"
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/openbmc/u-boot/board/freescale/t208xqds/
H A Deth_t208xqds.c1 // SPDX-License-Identifier: GPL-2.0+
134 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_read()
136 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_read()
138 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t208xqds_mdio_read()
144 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_write()
146 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_write()
148 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t208xqds_mdio_write()
153 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_reset()
155 return priv->realbus->reset(priv->realbus); in t208xqds_mdio_reset()
165 return -1; in t208xqds_mdio_init()
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/openbmc/qemu/hw/riscv/
H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
100 void *fdt; in create_fdt() local
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
115 if (!fdt) { in create_fdt()
120 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); in create_fdt()
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/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
27 return in_le32(pcie->dbi + offset); in dbi_readl()
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
41 return in_le32(pcie->ctrl + offset); in ctrl_readl()
47 if (pcie->big_endian) in ctrl_writel()
48 out_be32(pcie->ctrl + offset, value); in ctrl_writel()
50 out_le32(pcie->ctrl + offset, value); in ctrl_writel()
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * include/asm-arm/macro.h
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
24 * caches are enabled or on a multi-core system.
81 * Branch if current processor is a Cortex-A57 core.
87 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
92 * Branch if current processor is a Cortex-A53 core.
98 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
108 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
130 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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