Lines Matching +full:- +full:- +full:disable +full:- +full:fdt
1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
58 reg = readl(plat->regs + plat->ctl_reg); in socfpga_a10_clk_get_upstream()
61 if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) { in socfpga_a10_clk_get_upstream()
64 } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) { in socfpga_a10_clk_get_upstream()
73 dev_err(clk->dev, "Invalid clock source\n"); in socfpga_a10_clk_get_upstream()
74 return -EINVAL; in socfpga_a10_clk_get_upstream()
77 *upclk = &plat->clks.clks[reg]; in socfpga_a10_clk_get_upstream()
83 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_endisable()
87 if (!enable && plat->gate_reg) in socfpga_a10_clk_endisable()
88 clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit)); in socfpga_a10_clk_endisable()
101 if (enable && plat->gate_reg) in socfpga_a10_clk_endisable()
102 setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit)); in socfpga_a10_clk_endisable()
119 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_rate()
130 if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) { in socfpga_a10_clk_get_rate()
131 reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */ in socfpga_a10_clk_get_rate()
138 } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) { in socfpga_a10_clk_get_rate()
139 reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */ in socfpga_a10_clk_get_rate()
147 rate /= plat->fix_div; in socfpga_a10_clk_get_rate()
149 if (plat->fix_div == 1 && plat->ctl_reg) { in socfpga_a10_clk_get_rate()
150 reg = readl(plat->regs + plat->ctl_reg); in socfpga_a10_clk_get_rate()
155 if (plat->div_reg) { in socfpga_a10_clk_get_rate()
156 reg = readl(plat->regs + plat->div_reg); in socfpga_a10_clk_get_rate()
157 reg >>= plat->div_off; in socfpga_a10_clk_get_rate()
158 reg &= (1 << plat->div_len) - 1; in socfpga_a10_clk_get_rate()
159 if (plat->type == SOCFPGA_A10_CLK_PERIP_CLK) in socfpga_a10_clk_get_rate()
161 if (plat->type == SOCFPGA_A10_CLK_GATE_CLK) in socfpga_a10_clk_get_rate()
171 .disable = socfpga_a10_clk_disable,
190 const void *fdt = gd->fdt_blob; in socfpga_a10_handoff_workaround() local
191 struct clk_bulk *bulk = &plat->clks; in socfpga_a10_handoff_workaround()
199 if (fdt_node_check_compatible(fdt, offset, "fixed-clock")) in socfpga_a10_handoff_workaround()
203 if (!strcmp(dev->name, socfpga_a10_fixedclk_map[i])) in socfpga_a10_handoff_workaround()
214 bulk->count = 1; in socfpga_a10_handoff_workaround()
215 bulk->clks = devm_kcalloc(dev, bulk->count, in socfpga_a10_handoff_workaround()
217 if (!bulk->clks) in socfpga_a10_handoff_workaround()
220 ret = clk_request(dev, &bulk->clks[0]); in socfpga_a10_handoff_workaround()
222 free(bulk->clks); in socfpga_a10_handoff_workaround()
227 const void *fdt = gd->fdt_blob; in socfpga_a10_clk_bind() local
229 bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC); in socfpga_a10_clk_bind()
233 for (offset = fdt_first_subnode(fdt, offset); in socfpga_a10_clk_bind()
235 offset = fdt_next_subnode(fdt, offset)) { in socfpga_a10_clk_bind()
236 name = fdt_get_name(fdt, offset, NULL); in socfpga_a10_clk_bind()
238 return -EINVAL; in socfpga_a10_clk_bind()
241 offset = fdt_first_subnode(fdt, offset); in socfpga_a10_clk_bind()
242 name = fdt_get_name(fdt, offset, NULL); in socfpga_a10_clk_bind()
244 return -EINVAL; in socfpga_a10_clk_bind()
247 /* Filter out supported sub-clock */ in socfpga_a10_clk_bind()
248 if (fdt_node_check_compatible(fdt, offset, in socfpga_a10_clk_bind()
249 "altr,socfpga-a10-pll-clock") && in socfpga_a10_clk_bind()
250 fdt_node_check_compatible(fdt, offset, in socfpga_a10_clk_bind()
251 "altr,socfpga-a10-perip-clk") && in socfpga_a10_clk_bind()
252 fdt_node_check_compatible(fdt, offset, in socfpga_a10_clk_bind()
253 "altr,socfpga-a10-gate-clk") && in socfpga_a10_clk_bind()
254 fdt_node_check_compatible(fdt, offset, "fixed-clock")) in socfpga_a10_clk_bind()
257 if (pre_reloc_only && !dm_fdt_pre_reloc(fdt, offset)) in socfpga_a10_clk_bind()
260 ret = device_bind_driver_to_node(dev, "clk-a10", name, in socfpga_a10_clk_bind()
273 const void *fdt = gd->fdt_blob; in socfpga_a10_clk_probe() local
276 clk_get_bulk(dev, &plat->clks); in socfpga_a10_clk_probe()
280 if (!fdt_node_check_compatible(fdt, offset, in socfpga_a10_clk_probe()
281 "altr,socfpga-a10-pll-clock")) { in socfpga_a10_clk_probe()
283 if (plat->clks.count == 3) in socfpga_a10_clk_probe()
284 plat->type = SOCFPGA_A10_CLK_MAIN_PLL; in socfpga_a10_clk_probe()
286 plat->type = SOCFPGA_A10_CLK_PER_PLL; in socfpga_a10_clk_probe()
287 } else if (!fdt_node_check_compatible(fdt, offset, in socfpga_a10_clk_probe()
288 "altr,socfpga-a10-perip-clk")) { in socfpga_a10_clk_probe()
289 plat->type = SOCFPGA_A10_CLK_PERIP_CLK; in socfpga_a10_clk_probe()
290 } else if (!fdt_node_check_compatible(fdt, offset, in socfpga_a10_clk_probe()
291 "altr,socfpga-a10-gate-clk")) { in socfpga_a10_clk_probe()
292 plat->type = SOCFPGA_A10_CLK_GATE_CLK; in socfpga_a10_clk_probe()
294 plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK; in socfpga_a10_clk_probe()
305 const void *fdt = gd->fdt_blob; in socfpga_a10_ofdata_to_platdata() local
312 if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) { in socfpga_a10_ofdata_to_platdata()
313 plat->regs = devfdt_get_addr(dev); in socfpga_a10_ofdata_to_platdata()
317 return -ENODEV; in socfpga_a10_ofdata_to_platdata()
321 return -EINVAL; in socfpga_a10_ofdata_to_platdata()
323 plat->ctl_reg = regs; in socfpga_a10_ofdata_to_platdata()
324 plat->regs = pplat->regs; in socfpga_a10_ofdata_to_platdata()
327 plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK; in socfpga_a10_ofdata_to_platdata()
329 plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1); in socfpga_a10_ofdata_to_platdata()
331 ret = dev_read_u32_array(dev, "div-reg", divreg, ARRAY_SIZE(divreg)); in socfpga_a10_ofdata_to_platdata()
333 plat->div_reg = divreg[0]; in socfpga_a10_ofdata_to_platdata()
334 plat->div_len = divreg[2]; in socfpga_a10_ofdata_to_platdata()
335 plat->div_off = divreg[1]; in socfpga_a10_ofdata_to_platdata()
338 ret = dev_read_u32_array(dev, "clk-gate", gatereg, ARRAY_SIZE(gatereg)); in socfpga_a10_ofdata_to_platdata()
340 plat->gate_reg = gatereg[0]; in socfpga_a10_ofdata_to_platdata()
341 plat->gate_bit = gatereg[1]; in socfpga_a10_ofdata_to_platdata()
348 { .compatible = "altr,clk-mgr" },
353 .name = "clk-a10",