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/openbmc/u-boot/drivers/ddr/microchip/
H A Dddr2_regs.h46 #define REFCNT_CLK(x) (x) argument
47 #define REFDLY_CLK(x) ((x) << 16) argument
48 #define MAX_PEND_REF(x) ((x) << 24) argument
51 #define PRECH_PWR_DN_ONLY(x) ((x) << 22) argument
52 #define SELF_REF_DLY(x) ((x) << 12) argument
53 #define PWR_DN_DLY(x) ((x) << 4) argument
54 #define EN_AUTO_SELF_REF(x) ((x) << 3) argument
55 #define EN_AUTO_PWR_DN(x) ((x) << 2) argument
56 #define ERR_CORR_EN(x) ((x) << 1) argument
57 #define ECC_EN(x) (x) argument
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/openbmc/u-boot/include/faraday/
H A Dftsdmc021.h42 #define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ argument
43 #define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ argument
44 #define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ argument
45 #define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ argument
46 #define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ argument
47 #define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) argument
52 #define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ argument
54 #define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) argument
56 #define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) argument
61 #define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ argument
[all …]
/openbmc/u-boot/include/u-boot/
H A Dvariadic-macro.h16 #define _VM_HELP_1(_call, x, ...) _call(x) argument
17 #define _VM_HELP_2(_call, x, ...) _call(x) _VM_HELP_1(_call, __VA_ARGS__) argument
18 #define _VM_HELP_3(_call, x, ...) _call(x) _VM_HELP_2(_call, __VA_ARGS__) argument
19 #define _VM_HELP_4(_call, x, ...) _call(x) _VM_HELP_3(_call, __VA_ARGS__) argument
20 #define _VM_HELP_5(_call, x, ...) _call(x) _VM_HELP_4(_call, __VA_ARGS__) argument
21 #define _VM_HELP_6(_call, x, ...) _call(x) _VM_HELP_5(_call, __VA_ARGS__) argument
22 #define _VM_HELP_7(_call, x, ...) _call(x) _VM_HELP_6(_call, __VA_ARGS__) argument
23 #define _VM_HELP_8(_call, x, ...) _call(x) _VM_HELP_7(_call, __VA_ARGS__) argument
24 #define _VM_HELP_9(_call, x, ...) _call(x) _VM_HELP_8(_call, __VA_ARGS__) argument
25 #define _VM_HELP_10(_call, x, ...) _call(x) _VM_HELP_9(_call, __VA_ARGS__) argument
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/openbmc/u-boot/arch/m68k/include/asm/
H A Dm520x.h13 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
14 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
15 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
20 #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) argument
21 #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) argument
22 #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) argument
24 #define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) argument
26 #define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) argument
27 #define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) argument
28 #define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) argument
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H A Dm5301x.h13 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
14 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
15 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
16 #define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) argument
17 #define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) argument
18 #define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) argument
23 #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) argument
24 #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) argument
25 #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) argument
26 #define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) argument
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H A Dm547x_8x.h19 #define XARB_CFG_PM(x) (((x)&0x00000003)<<5) argument
20 #define XARB_CFG_SP(x) (((x)&0x00000007)<<8) argument
46 #define XARB_SIGCAP_TT(x) ((x)&0x0000001F) argument
48 #define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7) argument
56 #define XARB_PRI_M0P(x) (((x)&0x00000007)<<0) argument
57 #define XARB_PRI_M2P(x) (((x)&0x00000007)<<8) argument
58 #define XARB_PRI_M3P(x) (((x)&0x00000007)<<12) argument
64 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0) argument
66 #define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4) argument
87 #define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0) argument
[all …]
H A Dm5235.h18 #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) argument
22 #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) argument
31 #define SCM_CWCR_CWT(x) (((x)&0x07)<<3) argument
38 #define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) argument
48 #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) argument
53 #define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) argument
54 #define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) argument
55 #define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) argument
56 #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) argument
88 #define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) argument
[all …]
/openbmc/u-boot/drivers/serial/
H A Darm_dcc.c29 #define write_dcc(x) \ argument
32 #define read_dcc(x) \ argument
35 #define status_dcc(x) \ argument
45 #define write_dcc(x) \ argument
48 #define read_dcc(x) \ argument
51 #define status_dcc(x) \ argument
61 #define write_dcc(x) \ argument
64 #define read_dcc(x) \ argument
67 #define status_dcc(x) \ argument
74 #define write_dcc(x) \ argument
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/openbmc/qemu/include/qemu/
H A Dlockable.h28 qemu_make_lockable(void *x, QemuLockable *lockable) in qemu_make_lockable()
38 qemu_null_lockable(void *x) in qemu_null_lockable()
66 #define QML_OBJ_(x, name) (&(QemuLockable) { \ in QML_FUNC_() argument
84 #define QEMU_MAKE_LOCKABLE(x) \ argument
101 #define QEMU_MAKE_LOCKABLE_NONNULL(x) \ argument
113 static inline void qemu_lockable_unlock(QemuLockable *x) in qemu_lockable_unlock()
118 static inline QemuLockable *qemu_lockable_auto_lock(QemuLockable *x) in qemu_lockable_auto_lock()
124 static inline void qemu_lockable_auto_unlock(QemuLockable *x) in qemu_lockable_auto_unlock()
133 #define WITH_QEMU_LOCK_GUARD_(x, var) \ argument
161 #define WITH_QEMU_LOCK_GUARD(x) \ argument
[all …]
/openbmc/u-boot/scripts/dtc/libfdt/
H A Dlibfdt_env.h72 #define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) argument
73 #define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) argument
74 #define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ argument
76 #define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ argument
81 static inline uint16_t fdt16_to_cpu(fdt16_t x) in fdt16_to_cpu()
85 static inline fdt16_t cpu_to_fdt16(uint16_t x) in cpu_to_fdt16()
90 static inline uint32_t fdt32_to_cpu(fdt32_t x) in fdt32_to_cpu()
94 static inline fdt32_t cpu_to_fdt32(uint32_t x) in cpu_to_fdt32()
99 static inline uint64_t fdt64_to_cpu(fdt64_t x) in fdt64_to_cpu()
103 static inline fdt64_t cpu_to_fdt64(uint64_t x) in cpu_to_fdt64()
/openbmc/qemu/hw/arm/
H A Dsmmuv3-internal.h358 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8) argument
359 #define CMD_NUM(x) extract32((x)->word[0], 12 , 5) argument
360 #define CMD_SCALE(x) extract32((x)->word[0], 20 , 5) argument
361 #define CMD_SSEC(x) extract32((x)->word[0], 10, 1) argument
362 #define CMD_SSV(x) extract32((x)->word[0], 11, 1) argument
363 #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1) argument
364 #define CMD_RESUME_AB(x) extract32((x)->word[0], 13, 1) argument
365 #define CMD_SYNC_CS(x) extract32((x)->word[0], 12, 2) argument
366 #define CMD_SSID(x) extract32((x)->word[0], 12, 20) argument
367 #define CMD_SID(x) ((x)->word[1]) argument
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) argument
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0) argument
16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) argument
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) argument
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) argument
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) argument
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) argument
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) argument
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) argument
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0) argument
16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) argument
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) argument
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) argument
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) argument
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) argument
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) argument
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) argument
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0) argument
16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) argument
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) argument
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) argument
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) argument
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) argument
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) argument
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_devcpu_gcb_miim_regs.h13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) argument
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0) argument
16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) argument
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) argument
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) argument
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) argument
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) argument
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) argument
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dsromc.h12 #define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) argument
13 #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ argument
15 #define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) argument
16 #define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) argument
18 #define SROMC_BC_TACS(x) (x << 28) /* address set-up */ argument
19 #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ argument
20 #define SROMC_BC_TACC(x) (x << 16) /* access cycle */ argument
21 #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ argument
22 #define SROMC_BC_TAH(x) (x << 8) /* address holding time */ argument
23 #define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ argument
[all …]
H A Dsystem.h64 #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) argument
67 #define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x)) argument
70 #define mrc_midr(x) __asm__ __volatile__ \ argument
74 #define mrc_mpafr(x) __asm__ __volatile__ \ argument
78 #define mrc_sctlr(x) __asm__ __volatile__ \ argument
82 #define mrc_auxr(x) __asm__ __volatile__ \ argument
86 #define mrc_l2_ctlr(x) __asm__ __volatile__ \ argument
90 #define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ argument
94 #define mcr_sctlr(x) __asm__ __volatile__ \ argument
98 #define mcr_auxr(x) __asm__ __volatile__ \ argument
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/openbmc/qemu/include/user/
H A Dguest-host.h32 static inline vaddr cpu_untagged_addr(CPUState *cs, vaddr x) in cpu_untagged_addr()
42 static inline void *g2h_untagged(vaddr x) in g2h_untagged()
47 static inline void *g2h(CPUState *cs, vaddr x) in g2h()
52 static inline bool guest_addr_valid_untagged(vaddr x) in guest_addr_valid_untagged()
62 #define h2g_valid(x) \ argument
65 #define h2g_nocheck(x) ({ \ argument
70 #define h2g(x) ({ \ argument
/openbmc/u-boot/examples/standalone/
H A Dstubs.c5 #define FO(x) offsetof(struct jt_funcs, x) argument
18 #define EXPORT_FUNC(f, a, x, ...) \ argument
31 #define EXPORT_FUNC(f, a, x, ...) \ argument
46 #define EXPORT_FUNC(f, a, x, ...) \ argument
59 #define EXPORT_FUNC(f, a, x, ...) \ argument
76 #define EXPORT_FUNC(f, a, x, ...) \ argument
92 #define EXPORT_FUNC(f, a, x, ...) \ argument
105 #define EXPORT_FUNC(f, a, x, ...) \ argument
121 #define EXPORT_FUNC(f, a, x, ...) \ argument
136 #define EXPORT_FUNC(f, a, x, ...) \ argument
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/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dflexcan.h31 #define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4) argument
33 #define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F) argument
37 #define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5) argument
41 #define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07) argument
43 #define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1) argument
48 #define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8) argument
53 #define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F) argument
57 #define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18) argument
59 #define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF) argument
106 #define CAN_MCR_MAXMB(x) ((x) & 0x0F) argument
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/openbmc/u-boot/include/
H A Dfsl_dspi.h37 #define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) argument
42 #define DSPI_MCR_PCSIS(x) (1 << (16 + (x))) argument
58 #define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8) argument
64 #define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16) argument
67 #define DSPI_CTAR(x) (0x0c + (x * 4)) argument
69 #define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27) argument
73 #define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22) argument
78 #define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20) argument
83 #define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18) argument
88 #define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16) argument
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dbyteorder.h14 static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) in ___arch__swab16()
23 #define __arch__swab16(x) ___arch__swab16(x) argument
25 static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) in ___arch__swab32()
35 #define __arch__swab32(x) ___arch__swab32(x) argument
39 static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) in ___arch__swab64()
51 #define __arch__swab64(x) ___arch__swab64(x) argument
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_devcpu_gcb_miim_regs.h15 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0) argument
17 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) (x ? BIT(31) : 0) argument
18 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25)) argument
19 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20)) argument
20 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4)) argument
21 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1)) argument
24 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0)) argument
/openbmc/u-boot/drivers/video/
H A Dfsl_dcu_fb.c18 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) argument
28 #define DCU_MODE_BLEND_ITER(x) ((x) << 20) argument
32 #define DCU_BGND_R(x) ((x) << 16) argument
33 #define DCU_BGND_G(x) ((x) << 8) argument
34 #define DCU_BGND_B(x) (x) argument
35 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) argument
36 #define DCU_DISP_SIZE_DELTA_X(x) (x) argument
37 #define DCU_HSYN_PARA_BP(x) ((x) << 22) argument
38 #define DCU_HSYN_PARA_PW(x) ((x) << 11) argument
39 #define DCU_HSYN_PARA_FP(x) (x) argument
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9_smc.h41 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) argument
42 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) argument
43 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) argument
44 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) argument
46 #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) argument
47 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) argument
48 #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) argument
49 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) argument
51 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) argument
52 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) argument
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