1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2327def50SWang Huan /*
3327def50SWang Huan * Copyright 2014 Freescale Semiconductor, Inc.
4327def50SWang Huan *
5327def50SWang Huan * FSL DCU Framebuffer driver
6327def50SWang Huan */
7327def50SWang Huan
8327def50SWang Huan #include <asm/io.h>
9327def50SWang Huan #include <common.h>
1077810e63SStefan Agner #include <fdt_support.h>
11327def50SWang Huan #include <fsl_dcu_fb.h>
12327def50SWang Huan #include <linux/fb.h>
13327def50SWang Huan #include <malloc.h>
14327def50SWang Huan #include <video_fb.h>
15327def50SWang Huan #include "videomodes.h"
16327def50SWang Huan
17327def50SWang Huan /* Convert the X,Y resolution pair into a single number */
18327def50SWang Huan #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
19327def50SWang Huan
20327def50SWang Huan #ifdef CONFIG_SYS_FSL_DCU_LE
21327def50SWang Huan #define dcu_read32 in_le32
22327def50SWang Huan #define dcu_write32 out_le32
23327def50SWang Huan #elif defined(CONFIG_SYS_FSL_DCU_BE)
24327def50SWang Huan #define dcu_read32 in_be32
25327def50SWang Huan #define dcu_write32 out_be32
26327def50SWang Huan #endif
27327def50SWang Huan
28327def50SWang Huan #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
29327def50SWang Huan #define DCU_MODE_RASTER_EN (1 << 14)
30327def50SWang Huan #define DCU_MODE_NORMAL 1
31327def50SWang Huan #define DCU_MODE_COLORBAR 3
32327def50SWang Huan #define DCU_BGND_R(x) ((x) << 16)
33327def50SWang Huan #define DCU_BGND_G(x) ((x) << 8)
34327def50SWang Huan #define DCU_BGND_B(x) (x)
35327def50SWang Huan #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
36327def50SWang Huan #define DCU_DISP_SIZE_DELTA_X(x) (x)
37327def50SWang Huan #define DCU_HSYN_PARA_BP(x) ((x) << 22)
38327def50SWang Huan #define DCU_HSYN_PARA_PW(x) ((x) << 11)
39327def50SWang Huan #define DCU_HSYN_PARA_FP(x) (x)
40327def50SWang Huan #define DCU_VSYN_PARA_BP(x) ((x) << 22)
41327def50SWang Huan #define DCU_VSYN_PARA_PW(x) ((x) << 11)
42327def50SWang Huan #define DCU_VSYN_PARA_FP(x) (x)
4332f26f56SStefan Agner #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
44327def50SWang Huan #define DCU_SYN_POL_NEG_REMAIN (0 << 5)
45327def50SWang Huan #define DCU_SYN_POL_INV_VS_LOW (1 << 1)
46327def50SWang Huan #define DCU_SYN_POL_INV_HS_LOW (1)
47327def50SWang Huan #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
48327def50SWang Huan #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
49327def50SWang Huan #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
50327def50SWang Huan #define DCU_UPDATE_MODE_MODE (1 << 31)
51327def50SWang Huan #define DCU_UPDATE_MODE_READREG (1 << 30)
52327def50SWang Huan
53327def50SWang Huan #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
54327def50SWang Huan #define DCU_CTRLDESCLN_1_WIDTH(x) (x)
55327def50SWang Huan #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
56327def50SWang Huan #define DCU_CTRLDESCLN_2_POSX(x) (x)
57327def50SWang Huan #define DCU_CTRLDESCLN_4_EN (1 << 31)
58327def50SWang Huan #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
59327def50SWang Huan #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
60327def50SWang Huan #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
61327def50SWang Huan #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
62327def50SWang Huan #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
63327def50SWang Huan #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
64327def50SWang Huan #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
65327def50SWang Huan #define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
66327def50SWang Huan #define DCU_CTRLDESCLN_4_AB(x) (x)
67327def50SWang Huan #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
68327def50SWang Huan #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
69327def50SWang Huan #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
70327def50SWang Huan #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
71327def50SWang Huan #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
72327def50SWang Huan #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
73327def50SWang Huan #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
74327def50SWang Huan #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
75327def50SWang Huan #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
76327def50SWang Huan #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
77327def50SWang Huan
78327def50SWang Huan #define BPP_16_RGB565 4
79327def50SWang Huan #define BPP_24_RGB888 5
80327def50SWang Huan #define BPP_32_ARGB8888 6
81327def50SWang Huan
8277810e63SStefan Agner DECLARE_GLOBAL_DATA_PTR;
8377810e63SStefan Agner
84327def50SWang Huan /*
85327def50SWang Huan * This setting is used for the TWR_LCD_RGB card
86327def50SWang Huan */
87327def50SWang Huan static struct fb_videomode fsl_dcu_mode_480_272 = {
88327def50SWang Huan .name = "480x272-60",
89327def50SWang Huan .refresh = 60,
90327def50SWang Huan .xres = 480,
91327def50SWang Huan .yres = 272,
92327def50SWang Huan .pixclock = 91996,
93327def50SWang Huan .left_margin = 2,
94327def50SWang Huan .right_margin = 2,
95327def50SWang Huan .upper_margin = 1,
96327def50SWang Huan .lower_margin = 1,
97327def50SWang Huan .hsync_len = 41,
98327def50SWang Huan .vsync_len = 2,
99327def50SWang Huan .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
100327def50SWang Huan .vmode = FB_VMODE_NONINTERLACED
101327def50SWang Huan };
102327def50SWang Huan
103327def50SWang Huan /*
104327def50SWang Huan * This setting is used for Siliconimage SiI9022A HDMI
105327def50SWang Huan */
1067a2d533eSStefan Agner static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
107327def50SWang Huan .name = "640x480-60",
108327def50SWang Huan .refresh = 60,
109327def50SWang Huan .xres = 640,
110327def50SWang Huan .yres = 480,
111327def50SWang Huan .pixclock = 39722,
112327def50SWang Huan .left_margin = 48,
113327def50SWang Huan .right_margin = 16,
114327def50SWang Huan .upper_margin = 33,
115327def50SWang Huan .lower_margin = 10,
116327def50SWang Huan .hsync_len = 96,
117327def50SWang Huan .vsync_len = 2,
118327def50SWang Huan .sync = 0,
119327def50SWang Huan .vmode = FB_VMODE_NONINTERLACED,
120327def50SWang Huan };
121327def50SWang Huan
1227a2d533eSStefan Agner static struct fb_videomode fsl_dcu_mode_640_480 = {
1237a2d533eSStefan Agner .name = "640x480-60",
1247a2d533eSStefan Agner .refresh = 60,
1257a2d533eSStefan Agner .xres = 640,
1267a2d533eSStefan Agner .yres = 480,
1277a2d533eSStefan Agner .pixclock = 25175,
1287a2d533eSStefan Agner .left_margin = 40,
1297a2d533eSStefan Agner .right_margin = 24,
1307a2d533eSStefan Agner .upper_margin = 32,
1317a2d533eSStefan Agner .lower_margin = 11,
1327a2d533eSStefan Agner .hsync_len = 96,
1337a2d533eSStefan Agner .vsync_len = 2,
1347a2d533eSStefan Agner .sync = 0,
1357a2d533eSStefan Agner .vmode = FB_VMODE_NONINTERLACED,
1367a2d533eSStefan Agner };
1377a2d533eSStefan Agner
1387a2d533eSStefan Agner static struct fb_videomode fsl_dcu_mode_800_480 = {
1397a2d533eSStefan Agner .name = "800x480-60",
1407a2d533eSStefan Agner .refresh = 60,
1417a2d533eSStefan Agner .xres = 800,
1427a2d533eSStefan Agner .yres = 480,
1437a2d533eSStefan Agner .pixclock = 33260,
1447a2d533eSStefan Agner .left_margin = 216,
1457a2d533eSStefan Agner .right_margin = 40,
1467a2d533eSStefan Agner .upper_margin = 35,
1477a2d533eSStefan Agner .lower_margin = 10,
1487a2d533eSStefan Agner .hsync_len = 128,
1497a2d533eSStefan Agner .vsync_len = 2,
1507a2d533eSStefan Agner .sync = 0,
1517a2d533eSStefan Agner .vmode = FB_VMODE_NONINTERLACED,
1527a2d533eSStefan Agner };
1537a2d533eSStefan Agner
1547a2d533eSStefan Agner static struct fb_videomode fsl_dcu_mode_1024_600 = {
1557a2d533eSStefan Agner .name = "1024x600-60",
1567a2d533eSStefan Agner .refresh = 60,
1577a2d533eSStefan Agner .xres = 1024,
1587a2d533eSStefan Agner .yres = 600,
1597a2d533eSStefan Agner .pixclock = 48000,
1607a2d533eSStefan Agner .left_margin = 104,
1617a2d533eSStefan Agner .right_margin = 43,
1627a2d533eSStefan Agner .upper_margin = 24,
1637a2d533eSStefan Agner .lower_margin = 20,
1647a2d533eSStefan Agner .hsync_len = 5,
1657a2d533eSStefan Agner .vsync_len = 5,
1667a2d533eSStefan Agner .sync = 0,
1677a2d533eSStefan Agner .vmode = FB_VMODE_NONINTERLACED,
1687a2d533eSStefan Agner };
1697a2d533eSStefan Agner
170327def50SWang Huan /*
171327def50SWang Huan * DCU register map
172327def50SWang Huan */
173327def50SWang Huan struct dcu_reg {
174327def50SWang Huan u32 desc_cursor[4];
175327def50SWang Huan u32 mode;
176327def50SWang Huan u32 bgnd;
177327def50SWang Huan u32 disp_size;
178327def50SWang Huan u32 hsyn_para;
179327def50SWang Huan u32 vsyn_para;
180327def50SWang Huan u32 synpol;
181327def50SWang Huan u32 threshold;
182327def50SWang Huan u32 int_status;
183327def50SWang Huan u32 int_mask;
184327def50SWang Huan u32 colbar[8];
185327def50SWang Huan u32 div_ratio;
186327def50SWang Huan u32 sign_calc[2];
187327def50SWang Huan u32 crc_val;
188327def50SWang Huan u8 res_064[0x6c-0x64];
189327def50SWang Huan u32 parr_err_status1;
190327def50SWang Huan u8 res_070[0x7c-0x70];
191327def50SWang Huan u32 parr_err_status3;
192327def50SWang Huan u32 mparr_err_status1;
193327def50SWang Huan u8 res_084[0x90-0x84];
194327def50SWang Huan u32 mparr_err_status3;
195327def50SWang Huan u32 threshold_inp_buf[2];
196327def50SWang Huan u8 res_09c[0xa0-0x9c];
197327def50SWang Huan u32 luma_comp;
198327def50SWang Huan u32 chroma_red;
199327def50SWang Huan u32 chroma_green;
200327def50SWang Huan u32 chroma_blue;
201327def50SWang Huan u32 crc_pos;
202327def50SWang Huan u32 lyr_intpol_en;
203327def50SWang Huan u32 lyr_luma_comp;
204327def50SWang Huan u32 lyr_chrm_red;
205327def50SWang Huan u32 lyr_chrm_grn;
206327def50SWang Huan u32 lyr_chrm_blue;
207327def50SWang Huan u8 res_0c4[0xcc-0xc8];
208327def50SWang Huan u32 update_mode;
209327def50SWang Huan u32 underrun;
210327def50SWang Huan u8 res_0d4[0x100-0xd4];
211327def50SWang Huan u32 gpr;
212327def50SWang Huan u32 slr_l[2];
213327def50SWang Huan u32 slr_disp_size;
214327def50SWang Huan u32 slr_hvsync_para;
215327def50SWang Huan u32 slr_pol;
216327def50SWang Huan u32 slr_l_transp[2];
217327def50SWang Huan u8 res_120[0x200-0x120];
218327def50SWang Huan u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
219327def50SWang Huan };
220327def50SWang Huan
221327def50SWang Huan static struct fb_info info;
222327def50SWang Huan
reset_total_layers(void)223327def50SWang Huan static void reset_total_layers(void)
224327def50SWang Huan {
225327def50SWang Huan struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
226327def50SWang Huan int i;
227327def50SWang Huan
228327def50SWang Huan for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
229327def50SWang Huan dcu_write32(®s->ctrldescl[i][0], 0);
230327def50SWang Huan dcu_write32(®s->ctrldescl[i][1], 0);
231327def50SWang Huan dcu_write32(®s->ctrldescl[i][2], 0);
232327def50SWang Huan dcu_write32(®s->ctrldescl[i][3], 0);
233327def50SWang Huan dcu_write32(®s->ctrldescl[i][4], 0);
234327def50SWang Huan dcu_write32(®s->ctrldescl[i][5], 0);
235327def50SWang Huan dcu_write32(®s->ctrldescl[i][6], 0);
236327def50SWang Huan dcu_write32(®s->ctrldescl[i][7], 0);
237327def50SWang Huan dcu_write32(®s->ctrldescl[i][8], 0);
238327def50SWang Huan dcu_write32(®s->ctrldescl[i][9], 0);
239327def50SWang Huan dcu_write32(®s->ctrldescl[i][10], 0);
240327def50SWang Huan }
241327def50SWang Huan }
242327def50SWang Huan
layer_ctrldesc_init(int index,u32 pixel_format)243327def50SWang Huan static int layer_ctrldesc_init(int index, u32 pixel_format)
244327def50SWang Huan {
245327def50SWang Huan struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
246327def50SWang Huan unsigned int bpp = BPP_24_RGB888;
247327def50SWang Huan
248327def50SWang Huan dcu_write32(®s->ctrldescl[index][0],
249327def50SWang Huan DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) |
250327def50SWang Huan DCU_CTRLDESCLN_1_WIDTH(info.var.xres));
251327def50SWang Huan
252327def50SWang Huan dcu_write32(®s->ctrldescl[index][1],
253327def50SWang Huan DCU_CTRLDESCLN_2_POSY(0) |
254327def50SWang Huan DCU_CTRLDESCLN_2_POSX(0));
255327def50SWang Huan
256327def50SWang Huan dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base);
257327def50SWang Huan
258327def50SWang Huan switch (pixel_format) {
259327def50SWang Huan case 16:
260327def50SWang Huan bpp = BPP_16_RGB565;
261327def50SWang Huan break;
262327def50SWang Huan case 24:
263327def50SWang Huan bpp = BPP_24_RGB888;
264327def50SWang Huan break;
265327def50SWang Huan case 32:
266327def50SWang Huan bpp = BPP_32_ARGB8888;
267327def50SWang Huan break;
268327def50SWang Huan default:
269327def50SWang Huan printf("unsupported color depth: %u\n", pixel_format);
270327def50SWang Huan }
271327def50SWang Huan
272327def50SWang Huan dcu_write32(®s->ctrldescl[index][3],
273327def50SWang Huan DCU_CTRLDESCLN_4_EN |
274327def50SWang Huan DCU_CTRLDESCLN_4_TRANS(0xff) |
275327def50SWang Huan DCU_CTRLDESCLN_4_BPP(bpp) |
276327def50SWang Huan DCU_CTRLDESCLN_4_AB(0));
277327def50SWang Huan
278327def50SWang Huan dcu_write32(®s->ctrldescl[index][4],
279327def50SWang Huan DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
280327def50SWang Huan DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
281327def50SWang Huan DCU_CTRLDESCLN_5_CKMAX_B(0xff));
282327def50SWang Huan dcu_write32(®s->ctrldescl[index][5],
283327def50SWang Huan DCU_CTRLDESCLN_6_CKMIN_R(0) |
284327def50SWang Huan DCU_CTRLDESCLN_6_CKMIN_G(0) |
285327def50SWang Huan DCU_CTRLDESCLN_6_CKMIN_B(0));
286327def50SWang Huan
287327def50SWang Huan dcu_write32(®s->ctrldescl[index][6],
288327def50SWang Huan DCU_CTRLDESCLN_7_TILE_VER(0) |
289327def50SWang Huan DCU_CTRLDESCLN_7_TILE_HOR(0));
290327def50SWang Huan
291327def50SWang Huan dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
292327def50SWang Huan dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
293327def50SWang Huan
294327def50SWang Huan return 0;
295327def50SWang Huan }
296327def50SWang Huan
fsl_dcu_init(unsigned int xres,unsigned int yres,unsigned int pixel_format)297327def50SWang Huan int fsl_dcu_init(unsigned int xres, unsigned int yres,
298327def50SWang Huan unsigned int pixel_format)
299327def50SWang Huan {
300327def50SWang Huan struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
301327def50SWang Huan unsigned int div, mode;
302327def50SWang Huan
303327def50SWang Huan info.screen_size =
304327def50SWang Huan info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
30577810e63SStefan Agner
30677810e63SStefan Agner if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
30777810e63SStefan Agner info.screen_size = 0;
30877810e63SStefan Agner return -ENOMEM;
30977810e63SStefan Agner }
31077810e63SStefan Agner
31177810e63SStefan Agner /* Reserve framebuffer at the end of memory */
31277810e63SStefan Agner gd->fb_base = gd->bd->bi_dram[0].start +
31377810e63SStefan Agner gd->bd->bi_dram[0].size - info.screen_size;
31477810e63SStefan Agner info.screen_base = (char *)gd->fb_base;
31577810e63SStefan Agner
316327def50SWang Huan memset(info.screen_base, 0, info.screen_size);
317327def50SWang Huan
318327def50SWang Huan reset_total_layers();
319327def50SWang Huan
320327def50SWang Huan dcu_write32(®s->disp_size,
321327def50SWang Huan DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
322327def50SWang Huan DCU_DISP_SIZE_DELTA_X(info.var.xres / 16));
323327def50SWang Huan
324327def50SWang Huan dcu_write32(®s->hsyn_para,
325327def50SWang Huan DCU_HSYN_PARA_BP(info.var.left_margin) |
326327def50SWang Huan DCU_HSYN_PARA_PW(info.var.hsync_len) |
327327def50SWang Huan DCU_HSYN_PARA_FP(info.var.right_margin));
328327def50SWang Huan
329327def50SWang Huan dcu_write32(®s->vsyn_para,
330327def50SWang Huan DCU_VSYN_PARA_BP(info.var.upper_margin) |
331327def50SWang Huan DCU_VSYN_PARA_PW(info.var.vsync_len) |
332327def50SWang Huan DCU_VSYN_PARA_FP(info.var.lower_margin));
333327def50SWang Huan
334327def50SWang Huan dcu_write32(®s->synpol,
335327def50SWang Huan DCU_SYN_POL_INV_PXCK_FALL |
336327def50SWang Huan DCU_SYN_POL_NEG_REMAIN |
337327def50SWang Huan DCU_SYN_POL_INV_VS_LOW |
338327def50SWang Huan DCU_SYN_POL_INV_HS_LOW);
339327def50SWang Huan
340327def50SWang Huan dcu_write32(®s->bgnd,
341327def50SWang Huan DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
342327def50SWang Huan
343327def50SWang Huan dcu_write32(®s->mode,
3447ce92a55SStefan Agner DCU_MODE_BLEND_ITER(2) |
345327def50SWang Huan DCU_MODE_RASTER_EN);
346327def50SWang Huan
347327def50SWang Huan dcu_write32(®s->threshold,
348327def50SWang Huan DCU_THRESHOLD_LS_BF_VS(0x3) |
349327def50SWang Huan DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
350327def50SWang Huan DCU_THRESHOLD_OUT_BUF_LOW(0));
351327def50SWang Huan
352327def50SWang Huan mode = dcu_read32(®s->mode);
353327def50SWang Huan dcu_write32(®s->mode, mode | DCU_MODE_NORMAL);
354327def50SWang Huan
355327def50SWang Huan layer_ctrldesc_init(0, pixel_format);
356327def50SWang Huan
35732f26f56SStefan Agner div = dcu_set_pixel_clock(info.var.pixclock);
35832f26f56SStefan Agner dcu_write32(®s->div_ratio, (div - 1));
35932f26f56SStefan Agner
36032f26f56SStefan Agner dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
36132f26f56SStefan Agner
362327def50SWang Huan return 0;
363327def50SWang Huan }
364327def50SWang Huan
board_get_usable_ram_top(ulong total_size)36577810e63SStefan Agner ulong board_get_usable_ram_top(ulong total_size)
36677810e63SStefan Agner {
36777810e63SStefan Agner return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
36877810e63SStefan Agner }
36977810e63SStefan Agner
video_hw_init(void)370327def50SWang Huan void *video_hw_init(void)
371327def50SWang Huan {
372327def50SWang Huan static GraphicDevice ctfb;
373327def50SWang Huan const char *options;
374327def50SWang Huan unsigned int depth = 0, freq = 0;
375327def50SWang Huan struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
376327def50SWang Huan
377327def50SWang Huan if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
378327def50SWang Huan &options))
379327def50SWang Huan return NULL;
380327def50SWang Huan
381327def50SWang Huan /* Find the monitor port, which is a required option */
382327def50SWang Huan if (!options)
383327def50SWang Huan return NULL;
384327def50SWang Huan if (strncmp(options, "monitor=", 8) != 0)
385327def50SWang Huan return NULL;
386327def50SWang Huan
387327def50SWang Huan switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) {
388327def50SWang Huan case RESOLUTION(480, 272):
389327def50SWang Huan fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
390327def50SWang Huan break;
391327def50SWang Huan case RESOLUTION(640, 480):
3927a2d533eSStefan Agner if (!strncmp(options, "monitor=hdmi", 12))
3937a2d533eSStefan Agner fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
3947a2d533eSStefan Agner else
395327def50SWang Huan fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
396327def50SWang Huan break;
3977a2d533eSStefan Agner case RESOLUTION(800, 480):
3987a2d533eSStefan Agner fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
3997a2d533eSStefan Agner break;
4007a2d533eSStefan Agner case RESOLUTION(1024, 600):
4017a2d533eSStefan Agner fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
4027a2d533eSStefan Agner break;
403327def50SWang Huan default:
404327def50SWang Huan printf("unsupported resolution %ux%u\n",
405327def50SWang Huan ctfb.winSizeX, ctfb.winSizeY);
406327def50SWang Huan }
407327def50SWang Huan
408327def50SWang Huan info.var.xres = fsl_dcu_mode_db->xres;
409327def50SWang Huan info.var.yres = fsl_dcu_mode_db->yres;
410327def50SWang Huan info.var.bits_per_pixel = 32;
411327def50SWang Huan info.var.pixclock = fsl_dcu_mode_db->pixclock;
412327def50SWang Huan info.var.left_margin = fsl_dcu_mode_db->left_margin;
413327def50SWang Huan info.var.right_margin = fsl_dcu_mode_db->right_margin;
414327def50SWang Huan info.var.upper_margin = fsl_dcu_mode_db->upper_margin;
415327def50SWang Huan info.var.lower_margin = fsl_dcu_mode_db->lower_margin;
416327def50SWang Huan info.var.hsync_len = fsl_dcu_mode_db->hsync_len;
417327def50SWang Huan info.var.vsync_len = fsl_dcu_mode_db->vsync_len;
418327def50SWang Huan info.var.sync = fsl_dcu_mode_db->sync;
419327def50SWang Huan info.var.vmode = fsl_dcu_mode_db->vmode;
420327def50SWang Huan info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
421327def50SWang Huan
422327def50SWang Huan if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY,
423327def50SWang Huan options + 8, fsl_dcu_mode_db) < 0)
424327def50SWang Huan return NULL;
425327def50SWang Huan
426327def50SWang Huan ctfb.frameAdrs = (unsigned int)info.screen_base;
427327def50SWang Huan ctfb.plnSizeX = ctfb.winSizeX;
428327def50SWang Huan ctfb.plnSizeY = ctfb.winSizeY;
429327def50SWang Huan
430327def50SWang Huan ctfb.gdfBytesPP = 4;
431327def50SWang Huan ctfb.gdfIndex = GDF_32BIT_X888RGB;
432327def50SWang Huan
433327def50SWang Huan ctfb.memSize = info.screen_size;
434327def50SWang Huan
435327def50SWang Huan return &ctfb;
436327def50SWang Huan }
43777810e63SStefan Agner
43877810e63SStefan Agner #if defined(CONFIG_OF_BOARD_SETUP)
fsl_dcu_fixedfb_setup(void * blob)43977810e63SStefan Agner int fsl_dcu_fixedfb_setup(void *blob)
44077810e63SStefan Agner {
44177810e63SStefan Agner u64 start, size;
44277810e63SStefan Agner int ret;
44377810e63SStefan Agner
44477810e63SStefan Agner start = gd->bd->bi_dram[0].start;
44577810e63SStefan Agner size = gd->bd->bi_dram[0].size - info.screen_size;
44677810e63SStefan Agner
44777810e63SStefan Agner /*
44877810e63SStefan Agner * Align size on section size (1 MiB).
44977810e63SStefan Agner */
45077810e63SStefan Agner size &= 0xfff00000;
45177810e63SStefan Agner ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
45277810e63SStefan Agner if (ret) {
45377810e63SStefan Agner eprintf("Cannot setup fb: Error reserving memory\n");
45477810e63SStefan Agner return ret;
45577810e63SStefan Agner }
45677810e63SStefan Agner
45777810e63SStefan Agner return 0;
45877810e63SStefan Agner }
45977810e63SStefan Agner #endif
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