42 #define FTSDMC021_TP1_TCL(x)	((x) & 0x3)		/* CAS Latency */  argument
43 #define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */  argument
44 #define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */  argument
45 #define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */  argument
46 #define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)	/* Precharge Cycle */  argument
47 #define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)  argument
52 #define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)	/* Refresh interval */  argument
54 #define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)  argument
56 #define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)  argument
61 #define FTSDMC021_CR1_BNKSIZE(x)	((x) & 0xf)		/* Bank Size  */  argument
62 #define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)	/* Bus Width  */  argument
63 #define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)	/* SDRAM Size */  argument
64 #define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)	/* Data Width */  argument
66 #define FTSDMC021_CR1_MA2T(x)		(1 << 16)  argument
68 #define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)  argument
88 #define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)  argument
93 #define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)  argument
94 #define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)  argument
95 #define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)  argument
96 #define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)  argument
97 #define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)  argument
98 #define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)  argument
99 #define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)  argument
100 #define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)  argument
105 #define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)  argument
111 #define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/  argument