44017c66 | 13-Aug-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/mips: Load PTE as DATA
PTE is not CODE so load it as normal DATA access.
Fixes: 074cfcb4da ("Implement hardware page table walker for MIPS32") Suggested-by: Richard Henderson <richard.hender
target/mips: Load PTE as DATA
PTE is not CODE so load it as normal DATA access.
Fixes: 074cfcb4da ("Implement hardware page table walker for MIPS32") Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240814090452.2591-4-philmd@linaro.org>
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7ce9760d | 13-Aug-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/mips: Use correct MMU index in get_pte()
When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill(
target/mips: Use correct MMU index in get_pte()
When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index()
Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM or SM, while we only expect KM or ERL.
Fix by propagating ptw_mmu_idx to get_pte(), and use the cpu_ld/st_code_mmu() API with the correct MemOpIdx.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Reported-by: Waldemar Brodkorb <wbx@uclibc-ng.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2470 Fixes: 4e999bf419 ("target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240814090452.2591-3-philmd@linaro.org>
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b254c342 | 10-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/tcg: Access tcg_cflags with getter / setter
Access the CPUState::tcg_cflags via tcg_cflags_has() and tcg_cflags_set() helpers.
Mechanical change using the following Coccinelle spatch script:
accel/tcg: Access tcg_cflags with getter / setter
Access the CPUState::tcg_cflags via tcg_cflags_has() and tcg_cflags_set() helpers.
Mechanical change using the following Coccinelle spatch script:
@@ expression cpu; expression flags; @@ - cpu->tcg_cflags & flags + tcg_cflags_has(cpu, flags)
@@ expression cpu; expression flags; @@ - (tcg_cflags_has(cpu, flags)) + tcg_cflags_has(cpu, flags)
@@ expression cpu; expression flags; @@ - cpu->tcg_cflags |= flags; + tcg_cflags_set(cpu, flags);
Then manually moving the declarations, and adding both tcg_cflags_has() and tcg_cflags_set() definitions.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-15-philmd@linaro.org>
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747448d1 | 09-Feb-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/mips: Remove the unused DisasContext::saar field
DisasContext::saar is not used, remove it.
Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@lin
target/mips: Remove the unused DisasContext::saar field
DisasContext::saar is not used, remove it.
Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-11-philmd@linaro.org>
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ee58fddc | 09-Feb-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/mips: Remove helpers accessing SAARI register
DisasContext::saar boolean is never set, so this code is not reachable. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Rev
target/mips: Remove helpers accessing SAARI register
DisasContext::saar boolean is never set, so this code is not reachable. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-9-philmd@linaro.org>
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18f86aec | 14-Sep-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/mips: Fix TX79 LQ/SQ opcodes
The base register address offset is *signed*.
Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-b
target/mips: Fix TX79 LQ/SQ opcodes
The base register address offset is *signed*.
Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914090447.12557-1-philmd@linaro.org>
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db646e83 | 06-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'
We already provide "hw/misc/mips_itu.h" to declare prototype related to MIPSITUState. Move itc_reconfigure() declaration there.
S
hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'
We already provide "hw/misc/mips_itu.h" to declare prototype related to MIPSITUState. Move itc_reconfigure() declaration there.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231009171443.12145-3-philmd@linaro.org>
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