1 /* 2 * QEMU PowerPC CPU QOM header (target agnostic) 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 #ifdef TARGET_PPC64 27 #define TYPE_POWERPC_CPU "powerpc64-cpu" 28 #else 29 #define TYPE_POWERPC_CPU "powerpc-cpu" 30 #endif 31 32 OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) 33 34 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU 35 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX 36 37 #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") 38 39 ObjectClass *ppc_cpu_class_by_name(const char *name); 40 41 typedef struct CPUArchState CPUPPCState; 42 typedef struct ppc_tb_t ppc_tb_t; 43 typedef struct ppc_dcr_t ppc_dcr_t; 44 45 /*****************************************************************************/ 46 /* MMU model */ 47 typedef enum powerpc_mmu_t powerpc_mmu_t; 48 enum powerpc_mmu_t { 49 POWERPC_MMU_UNKNOWN = 0x00000000, 50 /* Standard 32 bits PowerPC MMU */ 51 POWERPC_MMU_32B = 0x00000001, 52 /* PowerPC 6xx MMU with software TLB */ 53 POWERPC_MMU_SOFT_6xx = 0x00000002, 54 /* 55 * PowerPC 74xx MMU with software TLB (this has been 56 * disabled, see git history for more information. 57 * keywords: tlbld tlbli TLBMISS PTEHI PTELO) 58 */ 59 POWERPC_MMU_SOFT_74xx = 0x00000003, 60 /* PowerPC 4xx MMU with software TLB */ 61 POWERPC_MMU_SOFT_4xx = 0x00000004, 62 /* PowerPC MMU in real mode only */ 63 POWERPC_MMU_REAL = 0x00000006, 64 /* Freescale MPC8xx MMU model */ 65 POWERPC_MMU_MPC8xx = 0x00000007, 66 /* BookE MMU model */ 67 POWERPC_MMU_BOOKE = 0x00000008, 68 /* BookE 2.06 MMU model */ 69 POWERPC_MMU_BOOKE206 = 0x00000009, 70 #define POWERPC_MMU_64 0x00010000 71 /* 64 bits PowerPC MMU */ 72 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 73 /* Architecture 2.03 and later (has LPCR) */ 74 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 75 /* Architecture 2.06 variant */ 76 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 77 /* Architecture 2.07 variant */ 78 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 79 /* Architecture 3.00 variant */ 80 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 81 }; 82 83 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) 84 { 85 return mmu_model & POWERPC_MMU_64; 86 } 87 88 /*****************************************************************************/ 89 /* Exception model */ 90 typedef enum powerpc_excp_t powerpc_excp_t; 91 enum powerpc_excp_t { 92 POWERPC_EXCP_UNKNOWN = 0, 93 /* Standard PowerPC exception model */ 94 POWERPC_EXCP_STD, 95 /* PowerPC 40x exception model */ 96 POWERPC_EXCP_40x, 97 /* PowerPC 603/604/G2 exception model */ 98 POWERPC_EXCP_6xx, 99 /* PowerPC 7xx exception model */ 100 POWERPC_EXCP_7xx, 101 /* PowerPC 74xx exception model */ 102 POWERPC_EXCP_74xx, 103 /* BookE exception model */ 104 POWERPC_EXCP_BOOKE, 105 /* PowerPC 970 exception model */ 106 POWERPC_EXCP_970, 107 /* POWER7 exception model */ 108 POWERPC_EXCP_POWER7, 109 /* POWER8 exception model */ 110 POWERPC_EXCP_POWER8, 111 /* POWER9 exception model */ 112 POWERPC_EXCP_POWER9, 113 /* POWER10 exception model */ 114 POWERPC_EXCP_POWER10, 115 }; 116 117 /*****************************************************************************/ 118 /* PM instructions */ 119 typedef enum { 120 PPC_PM_DOZE, 121 PPC_PM_NAP, 122 PPC_PM_SLEEP, 123 PPC_PM_RVWINKLE, 124 PPC_PM_STOP, 125 } powerpc_pm_insn_t; 126 127 /*****************************************************************************/ 128 /* Input pins model */ 129 typedef enum powerpc_input_t powerpc_input_t; 130 enum powerpc_input_t { 131 PPC_FLAGS_INPUT_UNKNOWN = 0, 132 /* PowerPC 6xx bus */ 133 PPC_FLAGS_INPUT_6xx, 134 /* BookE bus */ 135 PPC_FLAGS_INPUT_BookE, 136 /* PowerPC 405 bus */ 137 PPC_FLAGS_INPUT_405, 138 /* PowerPC 970 bus */ 139 PPC_FLAGS_INPUT_970, 140 /* PowerPC POWER7 bus */ 141 PPC_FLAGS_INPUT_POWER7, 142 /* PowerPC POWER9 bus */ 143 PPC_FLAGS_INPUT_POWER9, 144 /* Freescale RCPU bus */ 145 PPC_FLAGS_INPUT_RCPU, 146 }; 147 148 typedef struct PPCHash64Options PPCHash64Options; 149 150 /** 151 * PowerPCCPUClass: 152 * @parent_realize: The parent class' realize handler. 153 * @parent_phases: The parent class' reset phase handlers. 154 * 155 * A PowerPC CPU model. 156 */ 157 struct PowerPCCPUClass { 158 /*< private >*/ 159 CPUClass parent_class; 160 /*< public >*/ 161 162 DeviceRealize parent_realize; 163 DeviceUnrealize parent_unrealize; 164 ResettablePhases parent_phases; 165 void (*parent_parse_features)(const char *type, char *str, Error **errp); 166 167 uint32_t pvr; 168 /* 169 * If @best is false, match if pcc is in the family of pvr 170 * Else match only if pcc is the best match for pvr in this family. 171 */ 172 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best); 173 uint64_t pcr_mask; /* Available bits in PCR register */ 174 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 175 uint32_t svr; 176 uint64_t insns_flags; 177 uint64_t insns_flags2; 178 uint64_t msr_mask; 179 uint64_t lpcr_mask; /* Available bits in the LPCR */ 180 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 181 powerpc_mmu_t mmu_model; 182 powerpc_excp_t excp_model; 183 powerpc_input_t bus_model; 184 uint32_t flags; 185 int bfd_mach; 186 uint32_t l1_dcache_size, l1_icache_size; 187 #ifndef CONFIG_USER_ONLY 188 unsigned int gdb_num_sprs; 189 const char *gdb_spr_xml; 190 #endif 191 const PPCHash64Options *hash64_opts; 192 struct ppc_radix_page_info *radix_page_info; 193 uint32_t lrg_decr_bits; 194 int n_host_threads; 195 void (*init_proc)(CPUPPCState *env); 196 int (*check_pow)(CPUPPCState *env); 197 }; 198 199 #ifndef CONFIG_USER_ONLY 200 typedef struct PPCTimebase { 201 uint64_t guest_timebase; 202 int64_t time_of_the_day_ns; 203 bool runstate_paused; 204 } PPCTimebase; 205 206 extern const VMStateDescription vmstate_ppc_timebase; 207 208 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 209 .name = (stringify(_field)), \ 210 .version_id = (_version), \ 211 .size = sizeof(PPCTimebase), \ 212 .vmsd = &vmstate_ppc_timebase, \ 213 .flags = VMS_STRUCT, \ 214 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 215 } 216 217 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 218 RunState state); 219 #endif 220 221 #endif 222