a7bb53b1 | 23-Oct-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant
Putting the pointer in the structure for command handling puts a single variable element inside an otherwise constant
hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant
Putting the pointer in the structure for command handling puts a single variable element inside an otherwise constant structure. Move it out as a directly passed variable and take the cxl_cmd structures constant.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Message-Id: <20231023160806.13206-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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45234c2d | 23-Oct-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.
As _Static_assert is a declaration, it can't follow a label until C23. Some older versions of GCC trip up on this one.
This check
hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.
As _Static_assert is a declaration, it can't follow a label until C23. Some older versions of GCC trip up on this one.
This check has no obvious purpose so just remove it.
Reported-by: Jeongtae Park <jtp.park@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023140210.3089-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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388d6b57 | 23-Oct-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Use switch statements for read and write of cachemem registers
Establishing that only register accesses of size 4 and 8 can occur using these functions requires looking at their callers. Mak
hw/cxl: Use switch statements for read and write of cachemem registers
Establishing that only register accesses of size 4 and 8 can occur using these functions requires looking at their callers. Make it easier to see that by using switch statements. Assertions are used to enforce that the register storage is of the matching size, allowing fixed values to be used for divisors of the array indices.
Suggested-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023140210.3089-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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e967413f | 13-Sep-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Support 4 HDM decoders at all levels of topology
Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP and CXL Type 3 end points.
Signed-off-by: Jonathan Cameron <Jonathan.Ca
hw/cxl: Support 4 HDM decoders at all levels of topology
Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP and CXL Type 3 end points.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230913132523.29780-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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61c44bcf | 13-Sep-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Fix and use same calculation for HDM decoder block size everywhere
In order to avoid having the size of the per HDM decoder register block repeated in lots of places, create the register def
hw/cxl: Fix and use same calculation for HDM decoder block size everywhere
In order to avoid having the size of the per HDM decoder register block repeated in lots of places, create the register definitions for HDM decoder 1 and use the offset between the first registers in HDM decoder 0 and HDM decoder 1 to establish the offset.
Calculate in each function as this is more obvious and leads to shorter line lengths than a single #define which would need a long name to be specific enough.
Note that the code currently only supports one decoder, so the bugs this fixes don't actually affect anything.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230913132523.29780-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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87de174a | 13-Sep-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Add utility functions decoder interleave ways and target count.
As an encoded version of these key configuration parameters is available in a register, provide functions to extract it again
hw/cxl: Add utility functions decoder interleave ways and target count.
As an encoded version of these key configuration parameters is available in a register, provide functions to extract it again so as to avoid the need for duplicating the storage.
Whilst here update the _enc() function to include additional values as defined in the CXL 3.0 specification. Whilst they are not currently used in the emulation, they may be in future and it is easier to compare with the specification if all values are covered.
Add a spec reference for cxl_interleave_ways_enc() for consistency with the target count equivalent (and because it's nice to know where the magic numbers come from).
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230913132523.29780-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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6676bb97 | 30-May-2023 |
Ira Weiny <ira.weiny@intel.com> |
hw/cxl/events: Add event interrupt support
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox commands. Enable those commands to control interrupts for each of the event log types.
hw/cxl/events: Add event interrupt support
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox commands. Enable those commands to control interrupts for each of the event log types.
Skip the standard input mailbox length on the Set command due to DCD being optional. Perform the checks separately.
Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230530133603.16934-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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22d7e3be | 30-May-2023 |
Ira Weiny <ira.weiny@intel.com> |
hw/cxl/events: Wire up get/clear event mailbox commands
CXL testing is benefited from an artificial event log injection mechanism.
Add an event log infrastructure to insert, get, and clear events f
hw/cxl/events: Wire up get/clear event mailbox commands
CXL testing is benefited from an artificial event log injection mechanism.
Add an event log infrastructure to insert, get, and clear events from the various logs available on a device.
Replace the stubbed out CXL Get/Clear Event mailbox commands with commands that operate on the new infrastructure.
Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230530133603.16934-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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2f6b8c8f | 30-May-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Move CXLRetCode definition to cxl_device.h
Following patches will need access to the mailbox return code type so move it to the header.
Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed
hw/cxl: Move CXLRetCode definition to cxl_device.h
Following patches will need access to the mailbox return code type so move it to the header.
Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230530133603.16934-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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d7b84ddc | 30-May-2023 |
Ira Weiny <ira.weiny@intel.com> |
hw/cxl/events: Add event status register
The device status register block was defined. However, there were no individual registers nor any data wired up.
Define the event status register [CXL 3.0;
hw/cxl/events: Add event status register
The device status register block was defined. However, there were no individual registers nor any data wired up.
Define the event status register [CXL 3.0; 8.2.8.3.1] as part of the device status register block. Wire up the register and initialize the event status for each log.
To support CXL 3.0 the version of the device status register block needs to be 2. Change the macro to allow for setting the version.
Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230530133603.16934-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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6bda41a6 | 26-May-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Add clear poison mailbox command support.
Current implementation is very simple so many of the corner cases do not exist (e.g. fragmenting larger poison list entries)
Reviewed-by: Fan Ni <f
hw/cxl: Add clear poison mailbox command support.
Current implementation is very simple so many of the corner cases do not exist (e.g. fragmenting larger poison list entries)
Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230526170010.574-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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ff04b207 | 26-May-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Add poison injection via the mailbox.
Very simple implementation to allow testing of corresponding kernel code. Note that for now we track each 64 byte section independently. Whilst a valid
hw/cxl: Add poison injection via the mailbox.
Very simple implementation to allow testing of corresponding kernel code. Note that for now we track each 64 byte section independently. Whilst a valid implementation choice, it may make sense to fuse entries so as to prove out more complex corners of the kernel code.
Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230526170010.574-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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9547754f | 26-May-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: QMP based poison injection support
Inject poison using QMP command cxl-inject-poison to add an entry to the poison list.
For now, the poison is not returned CXL.mem reads, but only via the
hw/cxl: QMP based poison injection support
Inject poison using QMP command cxl-inject-poison to add an entry to the poison list.
For now, the poison is not returned CXL.mem reads, but only via the mailbox command Get Poison List. So a normal memory read to an address that is on the poison list will not yet result in a synchronous exception (and similar for partial cacheline writes). That is left for a future patch.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here: https://lore.kernel.org/linux-cxl/cover.1665606782.git.alison.schofield@intel.com/
To inject poison using QMP (telnet to the QMP port) { "execute": "qmp_capabilities" }
{ "execute": "cxl-inject-poison", "arguments": { "path": "/machine/peripheral/cxl-pmem0", "start": 2048, "length": 256 } }
Adjusted to select a device on your machine.
Note that the poison list supported is kept short enough to avoid the complexity of state machine that is needed to handle the MORE flag.
Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230526170010.574-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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547a652f | 23-Apr-2023 |
Ira Weiny <ira.weiny@intel.com> |
hw/cxl: Introduce cxl_device_get_timestamp() utility function
There are new users of this functionality coming shortly so factor it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-b
hw/cxl: Introduce cxl_device_get_timestamp() utility function
There are new users of this functionality coming shortly so factor it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230423162013.4535-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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adacc814 | 21-Apr-2023 |
Gregory Price <gregory.price@memverge.com> |
hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region.
Two new properties have
hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization: [volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been deprecated and will default the memory region to a persistent memory region (although a user may assign the region to a ram or file backed region). It cannot be used in combination with the new [persistent-memdev] property.
Partitioning volatile memory from persistent memory is not yet supported.
Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
Signed-off-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230421160827.2227-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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823371a6 | 21-Apr-2023 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Fix incorrect reset of commit and associated clearing of committed.
The hardware clearing the commit bit is not spec compliant. Clearing of committed bit when commit is cleared is not specif
hw/cxl: Fix incorrect reset of commit and associated clearing of committed.
The hardware clearing the commit bit is not spec compliant. Clearing of committed bit when commit is cleared is not specifically stated in the CXL spec, but is the expected (and simplest) permitted behaviour so use that for QEMU emulation.
Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
-- v2: Picked up tags. Message-Id: <20230421135906.3515-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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