1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/char/parallel-isa.h" 34 #include "hw/loader.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "hw/pci/pcie_port.h" 41 #include "hw/qdev-properties.h" 42 #include "hw/i386/x86.h" 43 #include "hw/i386/pc.h" 44 #include "hw/i386/amd_iommu.h" 45 #include "hw/i386/intel_iommu.h" 46 #include "hw/display/ramfb.h" 47 #include "hw/firmware/smbios.h" 48 #include "hw/ide/pci.h" 49 #include "hw/ide/ahci.h" 50 #include "hw/intc/ioapic.h" 51 #include "hw/southbridge/ich9.h" 52 #include "hw/usb.h" 53 #include "hw/usb/hcd-uhci.h" 54 #include "qapi/error.h" 55 #include "qemu/error-report.h" 56 #include "sysemu/numa.h" 57 #include "hw/hyperv/vmbus-bridge.h" 58 #include "hw/mem/nvdimm.h" 59 #include "hw/i386/acpi-build.h" 60 61 /* ICH9 AHCI has 6 ports */ 62 #define MAX_SATA_PORTS 6 63 64 struct ehci_companions { 65 const char *name; 66 int func; 67 int port; 68 }; 69 70 static const struct ehci_companions ich9_1d[] = { 71 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 72 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 73 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 74 }; 75 76 static const struct ehci_companions ich9_1a[] = { 77 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 78 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 79 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 80 }; 81 82 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 83 { 84 const struct ehci_companions *comp; 85 PCIDevice *ehci, *uhci; 86 BusState *usbbus; 87 const char *name; 88 int i; 89 90 switch (slot) { 91 case 0x1d: 92 name = "ich9-usb-ehci1"; 93 comp = ich9_1d; 94 break; 95 case 0x1a: 96 name = "ich9-usb-ehci2"; 97 comp = ich9_1a; 98 break; 99 default: 100 return -1; 101 } 102 103 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 104 pci_realize_and_unref(ehci, bus, &error_fatal); 105 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 106 107 for (i = 0; i < 3; i++) { 108 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 109 comp[i].name); 110 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 111 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 112 pci_realize_and_unref(uhci, bus, &error_fatal); 113 } 114 return 0; 115 } 116 117 /* PC hardware initialisation */ 118 static void pc_q35_init(MachineState *machine) 119 { 120 PCMachineState *pcms = PC_MACHINE(machine); 121 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 122 X86MachineState *x86ms = X86_MACHINE(machine); 123 Q35PCIHost *q35_host; 124 PCIHostState *phb; 125 PCIBus *host_bus; 126 PCIDevice *lpc; 127 DeviceState *lpc_dev; 128 BusState *idebus[MAX_SATA_PORTS]; 129 ISADevice *rtc_state; 130 MemoryRegion *system_memory = get_system_memory(); 131 MemoryRegion *system_io = get_system_io(); 132 MemoryRegion *pci_memory; 133 MemoryRegion *rom_memory; 134 GSIState *gsi_state; 135 ISABus *isa_bus; 136 int i; 137 PCIDevice *ahci; 138 ram_addr_t lowmem; 139 DriveInfo *hd[MAX_SATA_PORTS]; 140 MachineClass *mc = MACHINE_GET_CLASS(machine); 141 bool acpi_pcihp; 142 bool keep_pci_slot_hpc; 143 uint64_t pci_hole64_size = 0; 144 145 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 146 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 147 * also known as MMCFG). 148 * If it doesn't, we need to split it in chunks below and above 4G. 149 * In any case, try to make sure that guest addresses aligned at 150 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 151 */ 152 if (machine->ram_size >= 0xb0000000) { 153 lowmem = 0x80000000; 154 } else { 155 lowmem = 0xb0000000; 156 } 157 158 /* Handle the machine opt max-ram-below-4g. It is basically doing 159 * min(qemu limit, user limit). 160 */ 161 if (!pcms->max_ram_below_4g) { 162 pcms->max_ram_below_4g = 4 * GiB; 163 } 164 if (lowmem > pcms->max_ram_below_4g) { 165 lowmem = pcms->max_ram_below_4g; 166 if (machine->ram_size - lowmem > lowmem && 167 lowmem & (1 * GiB - 1)) { 168 warn_report("There is possibly poor performance as the ram size " 169 " (0x%" PRIx64 ") is more then twice the size of" 170 " max-ram-below-4g (%"PRIu64") and" 171 " max-ram-below-4g is not a multiple of 1G.", 172 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 173 } 174 } 175 176 if (machine->ram_size >= lowmem) { 177 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 178 x86ms->below_4g_mem_size = lowmem; 179 } else { 180 x86ms->above_4g_mem_size = 0; 181 x86ms->below_4g_mem_size = machine->ram_size; 182 } 183 184 pc_machine_init_sgx_epc(pcms); 185 x86_cpus_init(x86ms, pcmc->default_cpu_version); 186 187 kvmclock_create(pcmc->kvmclock_create_always); 188 189 /* pci enabled */ 190 if (pcmc->pci_enabled) { 191 pci_memory = g_new(MemoryRegion, 1); 192 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 193 rom_memory = pci_memory; 194 } else { 195 pci_memory = NULL; 196 rom_memory = system_memory; 197 } 198 199 pc_guest_info_init(pcms); 200 201 if (pcmc->smbios_defaults) { 202 /* These values are guest ABI, do not change */ 203 smbios_set_defaults("QEMU", mc->desc, 204 mc->name, pcmc->smbios_legacy_mode, 205 pcmc->smbios_uuid_encoded, 206 pcms->smbios_entry_point_type); 207 } 208 209 /* create pci host bus */ 210 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 211 212 if (pcmc->pci_enabled) { 213 pci_hole64_size = object_property_get_uint(OBJECT(q35_host), 214 PCI_HOST_PROP_PCI_HOLE64_SIZE, 215 &error_abort); 216 } 217 218 /* allocate ram and load rom/bios */ 219 pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); 220 221 object_property_add_child(OBJECT(machine), "q35", OBJECT(q35_host)); 222 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 223 OBJECT(machine->ram), NULL); 224 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 225 OBJECT(pci_memory), NULL); 226 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 227 OBJECT(system_memory), NULL); 228 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 229 OBJECT(system_io), NULL); 230 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 231 x86ms->below_4g_mem_size, NULL); 232 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 233 x86ms->above_4g_mem_size, NULL); 234 /* pci */ 235 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 236 phb = PCI_HOST_BRIDGE(q35_host); 237 host_bus = phb->bus; 238 /* create ISA bus */ 239 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, 240 TYPE_ICH9_LPC_DEVICE); 241 qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", 242 x86_machine_is_smm_enabled(x86ms)); 243 pci_realize_and_unref(lpc, host_bus, &error_fatal); 244 245 rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 246 247 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 248 TYPE_HOTPLUG_HANDLER, 249 (Object **)&x86ms->acpi_dev, 250 object_property_allow_set_link, 251 OBJ_PROP_LINK_STRONG); 252 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 253 OBJECT(lpc), &error_abort); 254 255 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 256 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 257 NULL); 258 259 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 260 "x-keep-pci-slot-hpc", 261 NULL); 262 263 if (!keep_pci_slot_hpc && acpi_pcihp) { 264 object_register_sugar_prop(TYPE_PCIE_SLOT, 265 "x-do-not-expose-native-hotplug-cap", 266 "true", true); 267 } 268 269 /* irq lines */ 270 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 271 272 lpc_dev = DEVICE(lpc); 273 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 274 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 275 } 276 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 277 278 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 279 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 280 } 281 282 if (pcmc->pci_enabled) { 283 ioapic_init_gsi(gsi_state, "q35"); 284 } 285 286 if (tcg_enabled()) { 287 x86_register_ferr_irq(x86ms->gsi[13]); 288 } 289 290 assert(pcms->vmport != ON_OFF_AUTO__MAX); 291 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 292 pcms->vmport = ON_OFF_AUTO_ON; 293 } 294 295 /* init basic PC hardware */ 296 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 297 0xff0104); 298 299 if (pcms->sata_enabled) { 300 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 301 ahci = pci_create_simple_multifunction(host_bus, 302 PCI_DEVFN(ICH9_SATA1_DEV, 303 ICH9_SATA1_FUNC), 304 true, "ich9-ahci"); 305 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 306 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 307 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 308 ide_drive_get(hd, ahci_get_num_ports(ahci)); 309 ahci_ide_create_devs(ahci, hd); 310 } else { 311 idebus[0] = idebus[1] = NULL; 312 } 313 314 if (machine_usb(machine)) { 315 /* Should we create 6 UHCI according to ich9 spec? */ 316 ehci_create_ich9_with_companions(host_bus, 0x1d); 317 } 318 319 if (pcms->smbus_enabled) { 320 PCIDevice *smb; 321 322 /* TODO: Populate SPD eeprom data. */ 323 smb = pci_create_simple_multifunction(host_bus, 324 PCI_DEVFN(ICH9_SMB_DEV, 325 ICH9_SMB_FUNC), 326 true, TYPE_ICH9_SMB_DEVICE); 327 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 328 329 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 330 } 331 332 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 333 334 /* the rest devices to which pci devfn is automatically assigned */ 335 pc_vga_init(isa_bus, host_bus); 336 pc_nic_init(pcmc, isa_bus, host_bus); 337 338 if (machine->nvdimms_state->is_enabled) { 339 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 340 x86_nvdimm_acpi_dsmio, 341 x86ms->fw_cfg, OBJECT(pcms)); 342 } 343 } 344 345 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 346 static void pc_init_##suffix(MachineState *machine) \ 347 { \ 348 void (*compat)(MachineState *m) = (compatfn); \ 349 if (compat) { \ 350 compat(machine); \ 351 } \ 352 pc_q35_init(machine); \ 353 } \ 354 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 355 356 357 static void pc_q35_machine_options(MachineClass *m) 358 { 359 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 360 pcmc->pci_root_uid = 0; 361 pcmc->default_cpu_version = 1; 362 363 m->family = "pc_q35"; 364 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 365 m->units_per_default_bus = 1; 366 m->default_machine_opts = "firmware=bios-256k.bin"; 367 m->default_display = "std"; 368 m->default_nic = "e1000e"; 369 m->default_kernel_irqchip_split = false; 370 m->no_floppy = 1; 371 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 372 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 373 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 374 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 375 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 376 m->max_cpus = 288; 377 } 378 379 static void pc_q35_8_1_machine_options(MachineClass *m) 380 { 381 pc_q35_machine_options(m); 382 m->alias = "q35"; 383 } 384 385 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 386 pc_q35_8_1_machine_options); 387 388 static void pc_q35_8_0_machine_options(MachineClass *m) 389 { 390 pc_q35_8_1_machine_options(m); 391 m->alias = NULL; 392 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 393 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 394 } 395 396 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 397 pc_q35_8_0_machine_options); 398 399 static void pc_q35_7_2_machine_options(MachineClass *m) 400 { 401 pc_q35_8_0_machine_options(m); 402 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 403 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 404 } 405 406 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 407 pc_q35_7_2_machine_options); 408 409 static void pc_q35_7_1_machine_options(MachineClass *m) 410 { 411 pc_q35_7_2_machine_options(m); 412 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 413 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 414 } 415 416 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 417 pc_q35_7_1_machine_options); 418 419 static void pc_q35_7_0_machine_options(MachineClass *m) 420 { 421 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 422 pc_q35_7_1_machine_options(m); 423 pcmc->enforce_amd_1tb_hole = false; 424 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 425 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 426 } 427 428 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 429 pc_q35_7_0_machine_options); 430 431 static void pc_q35_6_2_machine_options(MachineClass *m) 432 { 433 pc_q35_7_0_machine_options(m); 434 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 435 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 436 } 437 438 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 439 pc_q35_6_2_machine_options); 440 441 static void pc_q35_6_1_machine_options(MachineClass *m) 442 { 443 pc_q35_6_2_machine_options(m); 444 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 445 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 446 m->smp_props.prefer_sockets = true; 447 } 448 449 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 450 pc_q35_6_1_machine_options); 451 452 static void pc_q35_6_0_machine_options(MachineClass *m) 453 { 454 pc_q35_6_1_machine_options(m); 455 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 456 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 457 } 458 459 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 460 pc_q35_6_0_machine_options); 461 462 static void pc_q35_5_2_machine_options(MachineClass *m) 463 { 464 pc_q35_6_0_machine_options(m); 465 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 466 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 467 } 468 469 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 470 pc_q35_5_2_machine_options); 471 472 static void pc_q35_5_1_machine_options(MachineClass *m) 473 { 474 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 475 476 pc_q35_5_2_machine_options(m); 477 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 478 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 479 pcmc->kvmclock_create_always = false; 480 pcmc->pci_root_uid = 1; 481 } 482 483 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 484 pc_q35_5_1_machine_options); 485 486 static void pc_q35_5_0_machine_options(MachineClass *m) 487 { 488 pc_q35_5_1_machine_options(m); 489 m->numa_mem_supported = true; 490 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 491 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 492 m->auto_enable_numa_with_memdev = false; 493 } 494 495 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 496 pc_q35_5_0_machine_options); 497 498 static void pc_q35_4_2_machine_options(MachineClass *m) 499 { 500 pc_q35_5_0_machine_options(m); 501 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 502 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 503 } 504 505 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 506 pc_q35_4_2_machine_options); 507 508 static void pc_q35_4_1_machine_options(MachineClass *m) 509 { 510 pc_q35_4_2_machine_options(m); 511 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 512 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 513 } 514 515 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 516 pc_q35_4_1_machine_options); 517 518 static void pc_q35_4_0_1_machine_options(MachineClass *m) 519 { 520 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 521 pc_q35_4_1_machine_options(m); 522 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 523 /* 524 * This is the default machine for the 4.0-stable branch. It is basically 525 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 526 * 4.0 compat props. 527 */ 528 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 529 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 530 } 531 532 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 533 pc_q35_4_0_1_machine_options); 534 535 static void pc_q35_4_0_machine_options(MachineClass *m) 536 { 537 pc_q35_4_0_1_machine_options(m); 538 m->default_kernel_irqchip_split = true; 539 /* Compat props are applied by the 4.0.1 machine */ 540 } 541 542 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 543 pc_q35_4_0_machine_options); 544 545 static void pc_q35_3_1_machine_options(MachineClass *m) 546 { 547 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 548 549 pc_q35_4_0_machine_options(m); 550 m->default_kernel_irqchip_split = false; 551 m->smbus_no_migration_support = true; 552 pcmc->pvh_enabled = false; 553 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 554 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 555 } 556 557 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 558 pc_q35_3_1_machine_options); 559 560 static void pc_q35_3_0_machine_options(MachineClass *m) 561 { 562 pc_q35_3_1_machine_options(m); 563 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 564 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 565 } 566 567 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 568 pc_q35_3_0_machine_options); 569 570 static void pc_q35_2_12_machine_options(MachineClass *m) 571 { 572 pc_q35_3_0_machine_options(m); 573 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 574 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 575 } 576 577 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 578 pc_q35_2_12_machine_options); 579 580 static void pc_q35_2_11_machine_options(MachineClass *m) 581 { 582 pc_q35_2_12_machine_options(m); 583 m->default_nic = "e1000"; 584 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 585 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 586 } 587 588 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 589 pc_q35_2_11_machine_options); 590 591 static void pc_q35_2_10_machine_options(MachineClass *m) 592 { 593 pc_q35_2_11_machine_options(m); 594 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 595 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 596 m->auto_enable_numa_with_memhp = false; 597 } 598 599 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 600 pc_q35_2_10_machine_options); 601 602 static void pc_q35_2_9_machine_options(MachineClass *m) 603 { 604 pc_q35_2_10_machine_options(m); 605 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 606 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 607 } 608 609 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 610 pc_q35_2_9_machine_options); 611 612 static void pc_q35_2_8_machine_options(MachineClass *m) 613 { 614 pc_q35_2_9_machine_options(m); 615 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 616 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 617 } 618 619 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 620 pc_q35_2_8_machine_options); 621 622 static void pc_q35_2_7_machine_options(MachineClass *m) 623 { 624 pc_q35_2_8_machine_options(m); 625 m->max_cpus = 255; 626 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 627 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 628 } 629 630 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 631 pc_q35_2_7_machine_options); 632 633 static void pc_q35_2_6_machine_options(MachineClass *m) 634 { 635 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 636 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 637 638 pc_q35_2_7_machine_options(m); 639 pcmc->legacy_cpu_hotplug = true; 640 x86mc->fwcfg_dma_enabled = false; 641 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 642 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 643 } 644 645 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 646 pc_q35_2_6_machine_options); 647 648 static void pc_q35_2_5_machine_options(MachineClass *m) 649 { 650 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 651 652 pc_q35_2_6_machine_options(m); 653 x86mc->save_tsc_khz = false; 654 m->legacy_fw_cfg_order = 1; 655 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 656 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 657 } 658 659 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 660 pc_q35_2_5_machine_options); 661 662 static void pc_q35_2_4_machine_options(MachineClass *m) 663 { 664 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 665 666 pc_q35_2_5_machine_options(m); 667 m->hw_version = "2.4.0"; 668 pcmc->broken_reserved_end = true; 669 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 670 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 671 } 672 673 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 674 pc_q35_2_4_machine_options); 675