treewide: change my e-mail address, fix my nameChange my e-mail address to kabel@kernel.org, and fix my name innon-code parts (add diacritical mark).Link: https://lkml.kernel.org/r/2021032517112
treewide: change my e-mail address, fix my nameChange my e-mail address to kabel@kernel.org, and fix my name innon-code parts (add diacritical mark).Link: https://lkml.kernel.org/r/20210325171123.28093-2-kabel@kernel.orgSigned-off-by: Marek Behún <kabel@kernel.org>Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>Cc: Jassi Brar <jassisinghbrar@gmail.com>Cc: Linus Walleij <linus.walleij@linaro.org>Cc: Pavel Machek <pavel@ucw.cz>Signed-off-by: Andrew Morton <akpm@linux-foundation.org>Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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dt-bindings: bus: ti-sysc: Add support for PRUSS SYSC typeThe PRUSS module has a SYSCFG which is unique. The SYSCFGhas two additional unique fields called STANDBY_INIT andSUB_MWAIT in addition to
dt-bindings: bus: ti-sysc: Add support for PRUSS SYSC typeThe PRUSS module has a SYSCFG which is unique. The SYSCFGhas two additional unique fields called STANDBY_INIT andSUB_MWAIT in addition to regular IDLE_MODE and STANDBY_MODEfields. Add the bindings for this new sysc type.Cc: Rob Herring <robh+dt@kernel.org>Signed-off-by: Roger Quadros <rogerq@ti.com>Signed-off-by: Suman Anna <s-anna@ti.com>Acked-by: Rob Herring <robh@kernel.org>Signed-off-by: Tony Lindgren <tony@atomide.com>
Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/latemvebu dt64 for 5.4 (part 2)Add support for Turris Mox board (Armada 3720 SoC based)* tag 'mvebu-dt64-5.4-2' of g
Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/latemvebu dt64 for 5.4 (part 2)Add support for Turris Mox board (Armada 3720 SoC based)* tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits) arm64: dts: marvell: add DTS for Turris Mox dt-bindings: marvell: document Turris Mox compatible arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl arm64: dts: marvell: Add cpu clock node on Armada 7K/8K arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes arm64: dts: marvell: Add CP110 COMPHY clocks arm64: dts: marvell: armada-37xx: add mailbox node dt-bindings: gpio: Document GPIOs via Moxtet bus drivers: gpio: Add support for GPIOs over Moxtet bus bus: moxtet: Add sysfs and debugfs documentation dt-bindings: bus: Document moxtet bus binding bus: Add support for Moxtet bus reset: Add support for resets provided by SCMI firmware: arm_scmi: Add RESET protocol in SCMI v2.0 dt-bindings: arm: Extend SCMI to support new reset protocol firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels ...Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptopSigned-off-by: Arnd Bergmann <arnd@arndb.de>
bus: Add support for Moxtet busOn the Turris Mox router different modules can be connected to the mainCPU board: currently a module with a SFP cage, a module with MiniPCIeconnector, a PCIe pass-t
bus: Add support for Moxtet busOn the Turris Mox router different modules can be connected to the mainCPU board: currently a module with a SFP cage, a module with MiniPCIeconnector, a PCIe pass-through MiniPCIe connector module, a 4-portswitch module, an 8-port switch module, and a 4-port USB3 module.For example: [CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]Each of this modules has an input and output shift register, and theseare connected via SPI to the CPU board.Via SPI we are able to discover which modules are connected, in whichorder, and we can also read some information about the modules (eg.their interrupt status), and configure them.From each module 8 bits can be read (of which low 4 bits identify themodule) and 8 bits can be written.For example from the module with a SFP cage we can read the LOS,TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE andRATE-SELECT signals.This driver creates a new bus type, called "moxtet". For each Mox moduleit finds via SPI, it creates a new device on the moxtet bus so thatdrivers can be written for them.It also implements a virtual interrupt controller for the modules whichsend their interrupt status over the SPI shift register. These modulesdo this in addition to sending their interrupt status via the sharedinterrupt line. When the shared interrupt is triggered, we read from theshift register and handle IRQs for all devices which are in interrupt.The topology of how Mox modules are connected can then be read bylisting /sys/bus/moxtet/devices.Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.czSigned-off-by: Marek Behún <marek.behun@nic.cz>Reviewed-by: Linus Walleij <linus.walleij@linaro.org>Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dt-bindings: ti-sysc: Add SPDX license identifierAdd the appropriate SPDX license identifier to the commonTI sysc bindings header file.Signed-off-by: Suman Anna <s-anna@ti.com>Acked-by: Roger Q
dt-bindings: ti-sysc: Add SPDX license identifierAdd the appropriate SPDX license identifier to the commonTI sysc bindings header file.Signed-off-by: Suman Anna <s-anna@ti.com>Acked-by: Roger Quadros <rogerq@ti.com>Signed-off-by: Tony Lindgren <tony@atomide.com>
bus: ti-sysc: Add support for using ti-sysc for MCAN on dra76xThe dra76x MCAN generic interconnect module has a its ownformat for the bits in the control registers.Therefore add a new module typ
bus: ti-sysc: Add support for using ti-sysc for MCAN on dra76xThe dra76x MCAN generic interconnect module has a its ownformat for the bits in the control registers.Therefore add a new module type, new regbits and new capabilitiesspecific to the MCAN module.Acked-by: Rob Herring <robh@kernel.org>CC: Tony Lindgren <tony@atomide.com>Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>Signed-off-by: Tony Lindgren <tony@atomide.com>
dt-bindings: ti-sysc: Update binding for timers and capabilitiesThe ti-sysc binding does not yet describe the capabilities of theinterconnect target module. So to make the ti-sysc binding usablef
dt-bindings: ti-sysc: Update binding for timers and capabilitiesThe ti-sysc binding does not yet describe the capabilities of theinterconnect target module. So to make the ti-sysc binding usablefor configuring the interconnect target module, we need to add fewmore properties:1. To detect between omap2 and omap4 timers, let's add compatibles for them for "ti,sysc-omap2-timer" and,sysc-omap4-timer". This makes it easier to pick up the already initialized system timers later on2. Let's add "ti,sysc-mask" for a mask of features supported by the interconnect target module. This describes what we have available in the various SYSCONFIG registers3. Let's add "ti,sysc-midle" and "ti,sysc-sidle" lists for the master and slave idle modes supported by the interconnect target module. These describe the values available for MIDLE and SIDLE bits in the SYSCONFIG registers4. Some interconnect target modules need a short delay after reset before they can be accessed, let's use "ti,sysc-delay-us" for that5. Let's add "ti,syss-mask" bit to describe the optional SYSSTATUS register bits for reset done bits6. Let's support the two existing custom quirk properties already listed in Documentation/devicetree/bindings/arm/omap/omap.txt for "ti,no-reset-on-init" and "ti,no-idle-on-init"7. And finally, let's add a header for the binding for the dts files and the driver to useCc: Benoît Cousson <bcousson@baylibre.com>Cc: Dave Gerlach <d-gerlach@ti.com>Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>Cc: Liam Girdwood <lgirdwood@gmail.com>Cc: Mark Brown <broonie@kernel.org>Cc: Mark Rutland <mark.rutland@arm.com>Cc: Mauro Carvalho Chehab <mchehab@kernel.org>Cc: Nishanth Menon <nm@ti.com>Cc: Matthijs van Duin <matthijsvanduin@gmail.com>Cc: Paul Walmsley <paul@pwsan.com>Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>Cc: Sakari Ailus <sakari.ailus@iki.fi>Cc: Suman Anna <s-anna@ti.com>Cc: Tero Kristo <t-kristo@ti.com>Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>Reviewed-by: Rob Herring <robh@kernel.org>Signed-off-by: Tony Lindgren <tony@atomide.com>