1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC handling, local APIC timers 4 * 5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * 7 * Fixes 8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9 * thanks to Eric Gilmore 10 * and Rolf G. Tews 11 * for testing these extensively. 12 * Maciej W. Rozycki : Various updates and fixes. 13 * Mikael Pettersson : Power Management for UP-APIC. 14 * Pavel Machek and 15 * Mikael Pettersson : PM converted to driver model. 16 */ 17 18 #include <linux/perf_event.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/acpi_pmtmr.h> 22 #include <linux/clockchips.h> 23 #include <linux/interrupt.h> 24 #include <linux/memblock.h> 25 #include <linux/ftrace.h> 26 #include <linux/ioport.h> 27 #include <linux/export.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/delay.h> 30 #include <linux/timex.h> 31 #include <linux/i8253.h> 32 #include <linux/dmar.h> 33 #include <linux/init.h> 34 #include <linux/cpu.h> 35 #include <linux/dmi.h> 36 #include <linux/smp.h> 37 #include <linux/mm.h> 38 39 #include <asm/trace/irq_vectors.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/perf_event.h> 42 #include <asm/x86_init.h> 43 #include <asm/pgalloc.h> 44 #include <linux/atomic.h> 45 #include <asm/mpspec.h> 46 #include <asm/i8259.h> 47 #include <asm/proto.h> 48 #include <asm/traps.h> 49 #include <asm/apic.h> 50 #include <asm/io_apic.h> 51 #include <asm/desc.h> 52 #include <asm/hpet.h> 53 #include <asm/mtrr.h> 54 #include <asm/time.h> 55 #include <asm/smp.h> 56 #include <asm/mce.h> 57 #include <asm/tsc.h> 58 #include <asm/hypervisor.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/intel-family.h> 61 #include <asm/irq_regs.h> 62 63 unsigned int num_processors; 64 65 unsigned disabled_cpus; 66 67 /* Processor that is doing the boot up */ 68 unsigned int boot_cpu_physical_apicid = -1U; 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70 71 u8 boot_cpu_apic_version; 72 73 /* 74 * The highest APIC ID seen during enumeration. 75 */ 76 static unsigned int max_physical_apicid; 77 78 /* 79 * Bitmask of physically existing CPUs: 80 */ 81 physid_mask_t phys_cpu_present_map; 82 83 /* 84 * Processor to be disabled specified by kernel parameter 85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86 * avoid undefined behaviour caused by sending INIT from AP to BSP. 87 */ 88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 89 90 /* 91 * This variable controls which CPUs receive external NMIs. By default, 92 * external NMIs are delivered only to the BSP. 93 */ 94 static int apic_extnmi = APIC_EXTNMI_BSP; 95 96 /* 97 * Map cpu index to physical APIC ID 98 */ 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105 106 #ifdef CONFIG_X86_32 107 108 /* 109 * On x86_32, the mapping between cpu and logical apicid may vary 110 * depending on apic in use. The following early percpu variable is 111 * used for the mapping. This is where the behaviors of x86_64 and 32 112 * actually diverge. Let's keep it ugly for now. 113 */ 114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 115 116 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 117 static int enabled_via_apicbase; 118 119 /* 120 * Handle interrupt mode configuration register (IMCR). 121 * This register controls whether the interrupt signals 122 * that reach the BSP come from the master PIC or from the 123 * local APIC. Before entering Symmetric I/O Mode, either 124 * the BIOS or the operating system must switch out of 125 * PIC Mode by changing the IMCR. 126 */ 127 static inline void imcr_pic_to_apic(void) 128 { 129 /* select IMCR register */ 130 outb(0x70, 0x22); 131 /* NMI and 8259 INTR go through APIC */ 132 outb(0x01, 0x23); 133 } 134 135 static inline void imcr_apic_to_pic(void) 136 { 137 /* select IMCR register */ 138 outb(0x70, 0x22); 139 /* NMI and 8259 INTR go directly to BSP */ 140 outb(0x00, 0x23); 141 } 142 #endif 143 144 /* 145 * Knob to control our willingness to enable the local APIC. 146 * 147 * +1=force-enable 148 */ 149 static int force_enable_local_apic __initdata; 150 151 /* 152 * APIC command line parameters 153 */ 154 static int __init parse_lapic(char *arg) 155 { 156 if (IS_ENABLED(CONFIG_X86_32) && !arg) 157 force_enable_local_apic = 1; 158 else if (arg && !strncmp(arg, "notscdeadline", 13)) 159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160 return 0; 161 } 162 early_param("lapic", parse_lapic); 163 164 #ifdef CONFIG_X86_64 165 static int apic_calibrate_pmtmr __initdata; 166 static __init int setup_apicpmtimer(char *s) 167 { 168 apic_calibrate_pmtmr = 1; 169 notsc_setup(NULL); 170 return 0; 171 } 172 __setup("apicpmtimer", setup_apicpmtimer); 173 #endif 174 175 unsigned long mp_lapic_addr; 176 int disable_apic; 177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 178 static int disable_apic_timer __initdata; 179 /* Local APIC timer works in C2 */ 180 int local_apic_timer_c2_ok; 181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182 183 /* 184 * Debug level, exported for io_apic.c 185 */ 186 int apic_verbosity; 187 188 int pic_mode; 189 190 /* Have we found an MP table */ 191 int smp_found_config; 192 193 static struct resource lapic_resource = { 194 .name = "Local APIC", 195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196 }; 197 198 unsigned int lapic_timer_period = 0; 199 200 static void apic_pm_activate(void); 201 202 static unsigned long apic_phys; 203 204 /* 205 * Get the LAPIC version 206 */ 207 static inline int lapic_get_version(void) 208 { 209 return GET_APIC_VERSION(apic_read(APIC_LVR)); 210 } 211 212 /* 213 * Check, if the APIC is integrated or a separate chip 214 */ 215 static inline int lapic_is_integrated(void) 216 { 217 return APIC_INTEGRATED(lapic_get_version()); 218 } 219 220 /* 221 * Check, whether this is a modern or a first generation APIC 222 */ 223 static int modern_apic(void) 224 { 225 /* AMD systems use old APIC versions, so check the CPU */ 226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227 boot_cpu_data.x86 >= 0xf) 228 return 1; 229 230 /* Hygon systems use modern APIC */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232 return 1; 233 234 return lapic_get_version() >= 0x14; 235 } 236 237 /* 238 * right after this call apic become NOOP driven 239 * so apic->write/read doesn't do anything 240 */ 241 static void __init apic_disable(void) 242 { 243 pr_info("APIC: switched to apic NOOP\n"); 244 apic = &apic_noop; 245 } 246 247 void native_apic_wait_icr_idle(void) 248 { 249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250 cpu_relax(); 251 } 252 253 u32 native_safe_apic_wait_icr_idle(void) 254 { 255 u32 send_status; 256 int timeout; 257 258 timeout = 0; 259 do { 260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261 if (!send_status) 262 break; 263 inc_irq_stat(icr_read_retry_count); 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 unsigned long flags; 273 274 local_irq_save(flags); 275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276 apic_write(APIC_ICR, low); 277 local_irq_restore(flags); 278 } 279 280 u64 native_apic_icr_read(void) 281 { 282 u32 icr1, icr2; 283 284 icr2 = apic_read(APIC_ICR2); 285 icr1 = apic_read(APIC_ICR); 286 287 return icr1 | ((u64)icr2 << 32); 288 } 289 290 #ifdef CONFIG_X86_32 291 /** 292 * get_physical_broadcast - Get number of physical broadcast IDs 293 */ 294 int get_physical_broadcast(void) 295 { 296 return modern_apic() ? 0xff : 0xf; 297 } 298 #endif 299 300 /** 301 * lapic_get_maxlvt - get the maximum number of local vector table entries 302 */ 303 int lapic_get_maxlvt(void) 304 { 305 /* 306 * - we always have APIC integrated on 64bit mode 307 * - 82489DXs do not report # of LVT entries 308 */ 309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310 } 311 312 /* 313 * Local APIC timer 314 */ 315 316 /* Clock divisor */ 317 #define APIC_DIVISOR 16 318 #define TSC_DIVISOR 8 319 320 /* 321 * This function sets up the local APIC timer, with a timeout of 322 * 'clocks' APIC bus clock. During calibration we actually call 323 * this function twice on the boot CPU, once with a bogus timeout 324 * value, second time for real. The other (noncalibrating) CPUs 325 * call this function only once, with the real, calibrated value. 326 * 327 * We do reads before writes even if unnecessary, to get around the 328 * P5 APIC double write bug. 329 */ 330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331 { 332 unsigned int lvtt_value, tmp_value; 333 334 lvtt_value = LOCAL_TIMER_VECTOR; 335 if (!oneshot) 336 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339 340 if (!lapic_is_integrated()) 341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342 343 if (!irqen) 344 lvtt_value |= APIC_LVT_MASKED; 345 346 apic_write(APIC_LVTT, lvtt_value); 347 348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 349 /* 350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 352 * According to Intel, MFENCE can do the serialization here. 353 */ 354 asm volatile("mfence" : : : "memory"); 355 356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 357 return; 358 } 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370 } 371 372 /* 373 * Setup extended LVT, AMD specific 374 * 375 * Software should use the LVT offsets the BIOS provides. The offsets 376 * are determined by the subsystems using it like those for MCE 377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378 * are supported. Beginning with family 10h at least 4 offsets are 379 * available. 380 * 381 * Since the offsets must be consistent for all cores, we keep track 382 * of the LVT offsets in software and reserve the offset for the same 383 * vector also to be used on other cores. An offset is freed by 384 * setting the entry to APIC_EILVT_MASKED. 385 * 386 * If the BIOS is right, there should be no conflicts. Otherwise a 387 * "[Firmware Bug]: ..." error message is generated. However, if 388 * software does not properly determines the offsets, it is not 389 * necessarily a BIOS bug. 390 */ 391 392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393 394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395 { 396 return (old & APIC_EILVT_MASKED) 397 || (new == APIC_EILVT_MASKED) 398 || ((new & ~APIC_EILVT_MASKED) == old); 399 } 400 401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402 { 403 unsigned int rsvd, vector; 404 405 if (offset >= APIC_EILVT_NR_MAX) 406 return ~0; 407 408 rsvd = atomic_read(&eilvt_offsets[offset]); 409 do { 410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 411 if (vector && !eilvt_entry_is_changeable(vector, new)) 412 /* may not change if vectors are different */ 413 return rsvd; 414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415 } while (rsvd != new); 416 417 rsvd &= ~APIC_EILVT_MASKED; 418 if (rsvd && rsvd != vector) 419 pr_info("LVT offset %d assigned for vector 0x%02x\n", 420 offset, rsvd); 421 422 return new; 423 } 424 425 /* 426 * If mask=1, the LVT entry does not generate interrupts while mask=0 427 * enables the vector. See also the BKDGs. Must be called with 428 * preemption disabled. 429 */ 430 431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 432 { 433 unsigned long reg = APIC_EILVTn(offset); 434 unsigned int new, old, reserved; 435 436 new = (mask << 16) | (msg_type << 8) | vector; 437 old = apic_read(reg); 438 reserved = reserve_eilvt_offset(offset, new); 439 440 if (reserved != new) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on another cpu\n", 444 smp_processor_id(), reg, offset, new, reserved); 445 return -EINVAL; 446 } 447 448 if (!eilvt_entry_is_changeable(old, new)) { 449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 450 "vector 0x%x, but the register is already in use for " 451 "vector 0x%x on this cpu\n", 452 smp_processor_id(), reg, offset, new, old); 453 return -EBUSY; 454 } 455 456 apic_write(reg, new); 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 461 462 /* 463 * Program the next event, relative to now 464 */ 465 static int lapic_next_event(unsigned long delta, 466 struct clock_event_device *evt) 467 { 468 apic_write(APIC_TMICT, delta); 469 return 0; 470 } 471 472 static int lapic_next_deadline(unsigned long delta, 473 struct clock_event_device *evt) 474 { 475 u64 tsc; 476 477 tsc = rdtsc(); 478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 479 return 0; 480 } 481 482 static int lapic_timer_shutdown(struct clock_event_device *evt) 483 { 484 unsigned int v; 485 486 /* Lapic used as dummy for broadcast ? */ 487 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 488 return 0; 489 490 v = apic_read(APIC_LVTT); 491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 492 apic_write(APIC_LVTT, v); 493 apic_write(APIC_TMICT, 0); 494 return 0; 495 } 496 497 static inline int 498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 499 { 500 /* Lapic used as dummy for broadcast ? */ 501 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 502 return 0; 503 504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 505 return 0; 506 } 507 508 static int lapic_timer_set_periodic(struct clock_event_device *evt) 509 { 510 return lapic_timer_set_periodic_oneshot(evt, false); 511 } 512 513 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 514 { 515 return lapic_timer_set_periodic_oneshot(evt, true); 516 } 517 518 /* 519 * Local APIC timer broadcast function 520 */ 521 static void lapic_timer_broadcast(const struct cpumask *mask) 522 { 523 #ifdef CONFIG_SMP 524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 525 #endif 526 } 527 528 529 /* 530 * The local apic timer can be used for any function which is CPU local. 531 */ 532 static struct clock_event_device lapic_clockevent = { 533 .name = "lapic", 534 .features = CLOCK_EVT_FEAT_PERIODIC | 535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 536 | CLOCK_EVT_FEAT_DUMMY, 537 .shift = 32, 538 .set_state_shutdown = lapic_timer_shutdown, 539 .set_state_periodic = lapic_timer_set_periodic, 540 .set_state_oneshot = lapic_timer_set_oneshot, 541 .set_state_oneshot_stopped = lapic_timer_shutdown, 542 .set_next_event = lapic_next_event, 543 .broadcast = lapic_timer_broadcast, 544 .rating = 100, 545 .irq = -1, 546 }; 547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 548 549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 551 552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 554 555 static u32 hsx_deadline_rev(void) 556 { 557 switch (boot_cpu_data.x86_stepping) { 558 case 0x02: return 0x3a; /* EP */ 559 case 0x04: return 0x0f; /* EX */ 560 } 561 562 return ~0U; 563 } 564 565 static u32 bdx_deadline_rev(void) 566 { 567 switch (boot_cpu_data.x86_stepping) { 568 case 0x02: return 0x00000011; 569 case 0x03: return 0x0700000e; 570 case 0x04: return 0x0f00000c; 571 case 0x05: return 0x0e000003; 572 } 573 574 return ~0U; 575 } 576 577 static u32 skx_deadline_rev(void) 578 { 579 switch (boot_cpu_data.x86_stepping) { 580 case 0x03: return 0x01000136; 581 case 0x04: return 0x02000014; 582 } 583 584 if (boot_cpu_data.x86_stepping > 4) 585 return 0; 586 587 return ~0U; 588 } 589 590 static const struct x86_cpu_id deadline_match[] = { 591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 595 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 599 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 602 603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 605 606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 608 609 {}, 610 }; 611 612 static void apic_check_deadline_errata(void) 613 { 614 const struct x86_cpu_id *m; 615 u32 rev; 616 617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 618 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 619 return; 620 621 m = x86_match_cpu(deadline_match); 622 if (!m) 623 return; 624 625 /* 626 * Function pointers will have the MSB set due to address layout, 627 * immediate revisions will not. 628 */ 629 if ((long)m->driver_data < 0) 630 rev = ((u32 (*)(void))(m->driver_data))(); 631 else 632 rev = (u32)m->driver_data; 633 634 if (boot_cpu_data.microcode >= rev) 635 return; 636 637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 639 "please update microcode to version: 0x%x (or later)\n", rev); 640 } 641 642 /* 643 * Setup the local APIC timer for this CPU. Copy the initialized values 644 * of the boot CPU and register the clock event in the framework. 645 */ 646 static void setup_APIC_timer(void) 647 { 648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 649 650 if (this_cpu_has(X86_FEATURE_ARAT)) { 651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 652 /* Make LAPIC timer preferrable over percpu HPET */ 653 lapic_clockevent.rating = 150; 654 } 655 656 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 657 levt->cpumask = cpumask_of(smp_processor_id()); 658 659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 660 levt->name = "lapic-deadline"; 661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 662 CLOCK_EVT_FEAT_DUMMY); 663 levt->set_next_event = lapic_next_deadline; 664 clockevents_config_and_register(levt, 665 tsc_khz * (1000 / TSC_DIVISOR), 666 0xF, ~0UL); 667 } else 668 clockevents_register_device(levt); 669 } 670 671 /* 672 * Install the updated TSC frequency from recalibration at the TSC 673 * deadline clockevent devices. 674 */ 675 static void __lapic_update_tsc_freq(void *info) 676 { 677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 678 679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 680 return; 681 682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 683 } 684 685 void lapic_update_tsc_freq(void) 686 { 687 /* 688 * The clockevent device's ->mult and ->shift can both be 689 * changed. In order to avoid races, schedule the frequency 690 * update code on each CPU. 691 */ 692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 693 } 694 695 /* 696 * In this functions we calibrate APIC bus clocks to the external timer. 697 * 698 * We want to do the calibration only once since we want to have local timer 699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 700 * frequency. 701 * 702 * This was previously done by reading the PIT/HPET and waiting for a wrap 703 * around to find out, that a tick has elapsed. I have a box, where the PIT 704 * readout is broken, so it never gets out of the wait loop again. This was 705 * also reported by others. 706 * 707 * Monitoring the jiffies value is inaccurate and the clockevents 708 * infrastructure allows us to do a simple substitution of the interrupt 709 * handler. 710 * 711 * The calibration routine also uses the pm_timer when possible, as the PIT 712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 713 * back to normal later in the boot process). 714 */ 715 716 #define LAPIC_CAL_LOOPS (HZ/10) 717 718 static __initdata int lapic_cal_loops = -1; 719 static __initdata long lapic_cal_t1, lapic_cal_t2; 720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 723 724 /* 725 * Temporary interrupt handler and polled calibration function. 726 */ 727 static void __init lapic_cal_handler(struct clock_event_device *dev) 728 { 729 unsigned long long tsc = 0; 730 long tapic = apic_read(APIC_TMCCT); 731 unsigned long pm = acpi_pm_read_early(); 732 733 if (boot_cpu_has(X86_FEATURE_TSC)) 734 tsc = rdtsc(); 735 736 switch (lapic_cal_loops++) { 737 case 0: 738 lapic_cal_t1 = tapic; 739 lapic_cal_tsc1 = tsc; 740 lapic_cal_pm1 = pm; 741 lapic_cal_j1 = jiffies; 742 break; 743 744 case LAPIC_CAL_LOOPS: 745 lapic_cal_t2 = tapic; 746 lapic_cal_tsc2 = tsc; 747 if (pm < lapic_cal_pm1) 748 pm += ACPI_PM_OVRRUN; 749 lapic_cal_pm2 = pm; 750 lapic_cal_j2 = jiffies; 751 break; 752 } 753 } 754 755 static int __init 756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 757 { 758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 759 const long pm_thresh = pm_100ms / 100; 760 unsigned long mult; 761 u64 res; 762 763 #ifndef CONFIG_X86_PM_TIMER 764 return -1; 765 #endif 766 767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 768 769 /* Check, if the PM timer is available */ 770 if (!deltapm) 771 return -1; 772 773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 774 775 if (deltapm > (pm_100ms - pm_thresh) && 776 deltapm < (pm_100ms + pm_thresh)) { 777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 778 return 0; 779 } 780 781 res = (((u64)deltapm) * mult) >> 22; 782 do_div(res, 1000000); 783 pr_warning("APIC calibration not consistent " 784 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 785 786 /* Correct the lapic counter value */ 787 res = (((u64)(*delta)) * pm_100ms); 788 do_div(res, deltapm); 789 pr_info("APIC delta adjusted to PM-Timer: " 790 "%lu (%ld)\n", (unsigned long)res, *delta); 791 *delta = (long)res; 792 793 /* Correct the tsc counter value */ 794 if (boot_cpu_has(X86_FEATURE_TSC)) { 795 res = (((u64)(*deltatsc)) * pm_100ms); 796 do_div(res, deltapm); 797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 798 "PM-Timer: %lu (%ld)\n", 799 (unsigned long)res, *deltatsc); 800 *deltatsc = (long)res; 801 } 802 803 return 0; 804 } 805 806 static int __init lapic_init_clockevent(void) 807 { 808 if (!lapic_timer_period) 809 return -1; 810 811 /* Calculate the scaled math multiplication factor */ 812 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 813 TICK_NSEC, lapic_clockevent.shift); 814 lapic_clockevent.max_delta_ns = 815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 817 lapic_clockevent.min_delta_ns = 818 clockevent_delta2ns(0xF, &lapic_clockevent); 819 lapic_clockevent.min_delta_ticks = 0xF; 820 821 return 0; 822 } 823 824 bool __init apic_needs_pit(void) 825 { 826 /* 827 * If the frequencies are not known, PIT is required for both TSC 828 * and apic timer calibration. 829 */ 830 if (!tsc_khz || !cpu_khz) 831 return true; 832 833 /* Is there an APIC at all? */ 834 if (!boot_cpu_has(X86_FEATURE_APIC)) 835 return true; 836 837 /* Deadline timer is based on TSC so no further PIT action required */ 838 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 839 return false; 840 841 /* APIC timer disabled? */ 842 if (disable_apic_timer) 843 return true; 844 /* 845 * The APIC timer frequency is known already, no PIT calibration 846 * required. If unknown, let the PIT be initialized. 847 */ 848 return lapic_timer_period == 0; 849 } 850 851 static int __init calibrate_APIC_clock(void) 852 { 853 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 854 u64 tsc_perj = 0, tsc_start = 0; 855 unsigned long jif_start; 856 unsigned long deltaj; 857 long delta, deltatsc; 858 int pm_referenced = 0; 859 860 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 861 return 0; 862 863 /* 864 * Check if lapic timer has already been calibrated by platform 865 * specific routine, such as tsc calibration code. If so just fill 866 * in the clockevent structure and return. 867 */ 868 if (!lapic_init_clockevent()) { 869 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 870 lapic_timer_period); 871 /* 872 * Direct calibration methods must have an always running 873 * local APIC timer, no need for broadcast timer. 874 */ 875 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 876 return 0; 877 } 878 879 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 880 "calibrating APIC timer ...\n"); 881 882 /* 883 * There are platforms w/o global clockevent devices. Instead of 884 * making the calibration conditional on that, use a polling based 885 * approach everywhere. 886 */ 887 local_irq_disable(); 888 889 /* 890 * Setup the APIC counter to maximum. There is no way the lapic 891 * can underflow in the 100ms detection time frame 892 */ 893 __setup_APIC_LVTT(0xffffffff, 0, 0); 894 895 /* 896 * Methods to terminate the calibration loop: 897 * 1) Global clockevent if available (jiffies) 898 * 2) TSC if available and frequency is known 899 */ 900 jif_start = READ_ONCE(jiffies); 901 902 if (tsc_khz) { 903 tsc_start = rdtsc(); 904 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 905 } 906 907 /* 908 * Enable interrupts so the tick can fire, if a global 909 * clockevent device is available 910 */ 911 local_irq_enable(); 912 913 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 914 /* Wait for a tick to elapse */ 915 while (1) { 916 if (tsc_khz) { 917 u64 tsc_now = rdtsc(); 918 if ((tsc_now - tsc_start) >= tsc_perj) { 919 tsc_start += tsc_perj; 920 break; 921 } 922 } else { 923 unsigned long jif_now = READ_ONCE(jiffies); 924 925 if (time_after(jif_now, jif_start)) { 926 jif_start = jif_now; 927 break; 928 } 929 } 930 cpu_relax(); 931 } 932 933 /* Invoke the calibration routine */ 934 local_irq_disable(); 935 lapic_cal_handler(NULL); 936 local_irq_enable(); 937 } 938 939 local_irq_disable(); 940 941 /* Build delta t1-t2 as apic timer counts down */ 942 delta = lapic_cal_t1 - lapic_cal_t2; 943 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 944 945 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 946 947 /* we trust the PM based calibration if possible */ 948 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 949 &delta, &deltatsc); 950 951 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 952 lapic_init_clockevent(); 953 954 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 955 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 956 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 957 lapic_timer_period); 958 959 if (boot_cpu_has(X86_FEATURE_TSC)) { 960 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 961 "%ld.%04ld MHz.\n", 962 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 963 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 964 } 965 966 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 967 "%u.%04u MHz.\n", 968 lapic_timer_period / (1000000 / HZ), 969 lapic_timer_period % (1000000 / HZ)); 970 971 /* 972 * Do a sanity check on the APIC calibration result 973 */ 974 if (lapic_timer_period < (1000000 / HZ)) { 975 local_irq_enable(); 976 pr_warning("APIC frequency too slow, disabling apic timer\n"); 977 return -1; 978 } 979 980 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 981 982 /* 983 * PM timer calibration failed or not turned on so lets try APIC 984 * timer based calibration, if a global clockevent device is 985 * available. 986 */ 987 if (!pm_referenced && global_clock_event) { 988 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 989 990 /* 991 * Setup the apic timer manually 992 */ 993 levt->event_handler = lapic_cal_handler; 994 lapic_timer_set_periodic(levt); 995 lapic_cal_loops = -1; 996 997 /* Let the interrupts run */ 998 local_irq_enable(); 999 1000 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 1001 cpu_relax(); 1002 1003 /* Stop the lapic timer */ 1004 local_irq_disable(); 1005 lapic_timer_shutdown(levt); 1006 1007 /* Jiffies delta */ 1008 deltaj = lapic_cal_j2 - lapic_cal_j1; 1009 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 1010 1011 /* Check, if the jiffies result is consistent */ 1012 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 1013 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 1014 else 1015 levt->features |= CLOCK_EVT_FEAT_DUMMY; 1016 } 1017 local_irq_enable(); 1018 1019 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 1020 pr_warning("APIC timer disabled due to verification failure\n"); 1021 return -1; 1022 } 1023 1024 return 0; 1025 } 1026 1027 /* 1028 * Setup the boot APIC 1029 * 1030 * Calibrate and verify the result. 1031 */ 1032 void __init setup_boot_APIC_clock(void) 1033 { 1034 /* 1035 * The local apic timer can be disabled via the kernel 1036 * commandline or from the CPU detection code. Register the lapic 1037 * timer as a dummy clock event source on SMP systems, so the 1038 * broadcast mechanism is used. On UP systems simply ignore it. 1039 */ 1040 if (disable_apic_timer) { 1041 pr_info("Disabling APIC timer\n"); 1042 /* No broadcast on UP ! */ 1043 if (num_possible_cpus() > 1) { 1044 lapic_clockevent.mult = 1; 1045 setup_APIC_timer(); 1046 } 1047 return; 1048 } 1049 1050 if (calibrate_APIC_clock()) { 1051 /* No broadcast on UP ! */ 1052 if (num_possible_cpus() > 1) 1053 setup_APIC_timer(); 1054 return; 1055 } 1056 1057 /* 1058 * If nmi_watchdog is set to IO_APIC, we need the 1059 * PIT/HPET going. Otherwise register lapic as a dummy 1060 * device. 1061 */ 1062 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1063 1064 /* Setup the lapic or request the broadcast */ 1065 setup_APIC_timer(); 1066 amd_e400_c1e_apic_setup(); 1067 } 1068 1069 void setup_secondary_APIC_clock(void) 1070 { 1071 setup_APIC_timer(); 1072 amd_e400_c1e_apic_setup(); 1073 } 1074 1075 /* 1076 * The guts of the apic timer interrupt 1077 */ 1078 static void local_apic_timer_interrupt(void) 1079 { 1080 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1081 1082 /* 1083 * Normally we should not be here till LAPIC has been initialized but 1084 * in some cases like kdump, its possible that there is a pending LAPIC 1085 * timer interrupt from previous kernel's context and is delivered in 1086 * new kernel the moment interrupts are enabled. 1087 * 1088 * Interrupts are enabled early and LAPIC is setup much later, hence 1089 * its possible that when we get here evt->event_handler is NULL. 1090 * Check for event_handler being NULL and discard the interrupt as 1091 * spurious. 1092 */ 1093 if (!evt->event_handler) { 1094 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1095 smp_processor_id()); 1096 /* Switch it off */ 1097 lapic_timer_shutdown(evt); 1098 return; 1099 } 1100 1101 /* 1102 * the NMI deadlock-detector uses this. 1103 */ 1104 inc_irq_stat(apic_timer_irqs); 1105 1106 evt->event_handler(evt); 1107 } 1108 1109 /* 1110 * Local APIC timer interrupt. This is the most natural way for doing 1111 * local interrupts, but local timer interrupts can be emulated by 1112 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1113 * 1114 * [ if a single-CPU system runs an SMP kernel then we call the local 1115 * interrupt as well. Thus we cannot inline the local irq ... ] 1116 */ 1117 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1118 { 1119 struct pt_regs *old_regs = set_irq_regs(regs); 1120 1121 /* 1122 * NOTE! We'd better ACK the irq immediately, 1123 * because timer handling can be slow. 1124 * 1125 * update_process_times() expects us to have done irq_enter(). 1126 * Besides, if we don't timer interrupts ignore the global 1127 * interrupt lock, which is the WrongThing (tm) to do. 1128 */ 1129 entering_ack_irq(); 1130 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1131 local_apic_timer_interrupt(); 1132 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1133 exiting_irq(); 1134 1135 set_irq_regs(old_regs); 1136 } 1137 1138 int setup_profiling_timer(unsigned int multiplier) 1139 { 1140 return -EINVAL; 1141 } 1142 1143 /* 1144 * Local APIC start and shutdown 1145 */ 1146 1147 /** 1148 * clear_local_APIC - shutdown the local APIC 1149 * 1150 * This is called, when a CPU is disabled and before rebooting, so the state of 1151 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1152 * leftovers during boot. 1153 */ 1154 void clear_local_APIC(void) 1155 { 1156 int maxlvt; 1157 u32 v; 1158 1159 /* APIC hasn't been mapped yet */ 1160 if (!x2apic_mode && !apic_phys) 1161 return; 1162 1163 maxlvt = lapic_get_maxlvt(); 1164 /* 1165 * Masking an LVT entry can trigger a local APIC error 1166 * if the vector is zero. Mask LVTERR first to prevent this. 1167 */ 1168 if (maxlvt >= 3) { 1169 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1170 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1171 } 1172 /* 1173 * Careful: we have to set masks only first to deassert 1174 * any level-triggered sources. 1175 */ 1176 v = apic_read(APIC_LVTT); 1177 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1178 v = apic_read(APIC_LVT0); 1179 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1180 v = apic_read(APIC_LVT1); 1181 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1182 if (!x2apic_enabled()) { 1183 v = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1184 apic_write(APIC_LDR, v); 1185 } 1186 if (maxlvt >= 4) { 1187 v = apic_read(APIC_LVTPC); 1188 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1189 } 1190 1191 /* lets not touch this if we didn't frob it */ 1192 #ifdef CONFIG_X86_THERMAL_VECTOR 1193 if (maxlvt >= 5) { 1194 v = apic_read(APIC_LVTTHMR); 1195 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1196 } 1197 #endif 1198 #ifdef CONFIG_X86_MCE_INTEL 1199 if (maxlvt >= 6) { 1200 v = apic_read(APIC_LVTCMCI); 1201 if (!(v & APIC_LVT_MASKED)) 1202 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1203 } 1204 #endif 1205 1206 /* 1207 * Clean APIC state for other OSs: 1208 */ 1209 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1210 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1211 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1212 if (maxlvt >= 3) 1213 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1214 if (maxlvt >= 4) 1215 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1216 1217 /* Integrated APIC (!82489DX) ? */ 1218 if (lapic_is_integrated()) { 1219 if (maxlvt > 3) 1220 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1221 apic_write(APIC_ESR, 0); 1222 apic_read(APIC_ESR); 1223 } 1224 } 1225 1226 /** 1227 * disable_local_APIC - clear and disable the local APIC 1228 */ 1229 void disable_local_APIC(void) 1230 { 1231 unsigned int value; 1232 1233 /* APIC hasn't been mapped yet */ 1234 if (!x2apic_mode && !apic_phys) 1235 return; 1236 1237 clear_local_APIC(); 1238 1239 /* 1240 * Disable APIC (implies clearing of registers 1241 * for 82489DX!). 1242 */ 1243 value = apic_read(APIC_SPIV); 1244 value &= ~APIC_SPIV_APIC_ENABLED; 1245 apic_write(APIC_SPIV, value); 1246 1247 #ifdef CONFIG_X86_32 1248 /* 1249 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1250 * restore the disabled state. 1251 */ 1252 if (enabled_via_apicbase) { 1253 unsigned int l, h; 1254 1255 rdmsr(MSR_IA32_APICBASE, l, h); 1256 l &= ~MSR_IA32_APICBASE_ENABLE; 1257 wrmsr(MSR_IA32_APICBASE, l, h); 1258 } 1259 #endif 1260 } 1261 1262 /* 1263 * If Linux enabled the LAPIC against the BIOS default disable it down before 1264 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1265 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1266 * for the case where Linux didn't enable the LAPIC. 1267 */ 1268 void lapic_shutdown(void) 1269 { 1270 unsigned long flags; 1271 1272 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1273 return; 1274 1275 local_irq_save(flags); 1276 1277 #ifdef CONFIG_X86_32 1278 if (!enabled_via_apicbase) 1279 clear_local_APIC(); 1280 else 1281 #endif 1282 disable_local_APIC(); 1283 1284 1285 local_irq_restore(flags); 1286 } 1287 1288 /** 1289 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1290 */ 1291 void __init sync_Arb_IDs(void) 1292 { 1293 /* 1294 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1295 * needed on AMD. 1296 */ 1297 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1298 return; 1299 1300 /* 1301 * Wait for idle. 1302 */ 1303 apic_wait_icr_idle(); 1304 1305 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1306 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1307 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1308 } 1309 1310 enum apic_intr_mode_id apic_intr_mode; 1311 1312 static int __init apic_intr_mode_select(void) 1313 { 1314 /* Check kernel option */ 1315 if (disable_apic) { 1316 pr_info("APIC disabled via kernel command line\n"); 1317 return APIC_PIC; 1318 } 1319 1320 /* Check BIOS */ 1321 #ifdef CONFIG_X86_64 1322 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1323 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1324 disable_apic = 1; 1325 pr_info("APIC disabled by BIOS\n"); 1326 return APIC_PIC; 1327 } 1328 #else 1329 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1330 1331 /* Neither 82489DX nor integrated APIC ? */ 1332 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1333 disable_apic = 1; 1334 return APIC_PIC; 1335 } 1336 1337 /* If the BIOS pretends there is an integrated APIC ? */ 1338 if (!boot_cpu_has(X86_FEATURE_APIC) && 1339 APIC_INTEGRATED(boot_cpu_apic_version)) { 1340 disable_apic = 1; 1341 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1342 boot_cpu_physical_apicid); 1343 return APIC_PIC; 1344 } 1345 #endif 1346 1347 /* Check MP table or ACPI MADT configuration */ 1348 if (!smp_found_config) { 1349 disable_ioapic_support(); 1350 if (!acpi_lapic) { 1351 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1352 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1353 } 1354 return APIC_VIRTUAL_WIRE; 1355 } 1356 1357 #ifdef CONFIG_SMP 1358 /* If SMP should be disabled, then really disable it! */ 1359 if (!setup_max_cpus) { 1360 pr_info("APIC: SMP mode deactivated\n"); 1361 return APIC_SYMMETRIC_IO_NO_ROUTING; 1362 } 1363 1364 if (read_apic_id() != boot_cpu_physical_apicid) { 1365 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1366 read_apic_id(), boot_cpu_physical_apicid); 1367 /* Or can we switch back to PIC here? */ 1368 } 1369 #endif 1370 1371 return APIC_SYMMETRIC_IO; 1372 } 1373 1374 /* 1375 * An initial setup of the virtual wire mode. 1376 */ 1377 void __init init_bsp_APIC(void) 1378 { 1379 unsigned int value; 1380 1381 /* 1382 * Don't do the setup now if we have a SMP BIOS as the 1383 * through-I/O-APIC virtual wire mode might be active. 1384 */ 1385 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1386 return; 1387 1388 /* 1389 * Do not trust the local APIC being empty at bootup. 1390 */ 1391 clear_local_APIC(); 1392 1393 /* 1394 * Enable APIC. 1395 */ 1396 value = apic_read(APIC_SPIV); 1397 value &= ~APIC_VECTOR_MASK; 1398 value |= APIC_SPIV_APIC_ENABLED; 1399 1400 #ifdef CONFIG_X86_32 1401 /* This bit is reserved on P4/Xeon and should be cleared */ 1402 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1403 (boot_cpu_data.x86 == 15)) 1404 value &= ~APIC_SPIV_FOCUS_DISABLED; 1405 else 1406 #endif 1407 value |= APIC_SPIV_FOCUS_DISABLED; 1408 value |= SPURIOUS_APIC_VECTOR; 1409 apic_write(APIC_SPIV, value); 1410 1411 /* 1412 * Set up the virtual wire mode. 1413 */ 1414 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1415 value = APIC_DM_NMI; 1416 if (!lapic_is_integrated()) /* 82489DX */ 1417 value |= APIC_LVT_LEVEL_TRIGGER; 1418 if (apic_extnmi == APIC_EXTNMI_NONE) 1419 value |= APIC_LVT_MASKED; 1420 apic_write(APIC_LVT1, value); 1421 } 1422 1423 static void __init apic_bsp_setup(bool upmode); 1424 1425 /* Init the interrupt delivery mode for the BSP */ 1426 void __init apic_intr_mode_init(void) 1427 { 1428 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1429 1430 apic_intr_mode = apic_intr_mode_select(); 1431 1432 switch (apic_intr_mode) { 1433 case APIC_PIC: 1434 pr_info("APIC: Keep in PIC mode(8259)\n"); 1435 return; 1436 case APIC_VIRTUAL_WIRE: 1437 pr_info("APIC: Switch to virtual wire mode setup\n"); 1438 default_setup_apic_routing(); 1439 break; 1440 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1441 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1442 upmode = true; 1443 default_setup_apic_routing(); 1444 break; 1445 case APIC_SYMMETRIC_IO: 1446 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1447 default_setup_apic_routing(); 1448 break; 1449 case APIC_SYMMETRIC_IO_NO_ROUTING: 1450 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1451 break; 1452 } 1453 1454 apic_bsp_setup(upmode); 1455 } 1456 1457 static void lapic_setup_esr(void) 1458 { 1459 unsigned int oldvalue, value, maxlvt; 1460 1461 if (!lapic_is_integrated()) { 1462 pr_info("No ESR for 82489DX.\n"); 1463 return; 1464 } 1465 1466 if (apic->disable_esr) { 1467 /* 1468 * Something untraceable is creating bad interrupts on 1469 * secondary quads ... for the moment, just leave the 1470 * ESR disabled - we can't do anything useful with the 1471 * errors anyway - mbligh 1472 */ 1473 pr_info("Leaving ESR disabled.\n"); 1474 return; 1475 } 1476 1477 maxlvt = lapic_get_maxlvt(); 1478 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1479 apic_write(APIC_ESR, 0); 1480 oldvalue = apic_read(APIC_ESR); 1481 1482 /* enables sending errors */ 1483 value = ERROR_APIC_VECTOR; 1484 apic_write(APIC_LVTERR, value); 1485 1486 /* 1487 * spec says clear errors after enabling vector. 1488 */ 1489 if (maxlvt > 3) 1490 apic_write(APIC_ESR, 0); 1491 value = apic_read(APIC_ESR); 1492 if (value != oldvalue) 1493 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1494 "vector: 0x%08x after: 0x%08x\n", 1495 oldvalue, value); 1496 } 1497 1498 static void apic_pending_intr_clear(void) 1499 { 1500 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1501 unsigned long long tsc = 0, ntsc; 1502 unsigned int queued; 1503 unsigned long value; 1504 int i, j, acked = 0; 1505 1506 if (boot_cpu_has(X86_FEATURE_TSC)) 1507 tsc = rdtsc(); 1508 /* 1509 * After a crash, we no longer service the interrupts and a pending 1510 * interrupt from previous kernel might still have ISR bit set. 1511 * 1512 * Most probably by now CPU has serviced that pending interrupt and 1513 * it might not have done the ack_APIC_irq() because it thought, 1514 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1515 * does not clear the ISR bit and cpu thinks it has already serivced 1516 * the interrupt. Hence a vector might get locked. It was noticed 1517 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1518 */ 1519 do { 1520 queued = 0; 1521 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1522 queued |= apic_read(APIC_IRR + i*0x10); 1523 1524 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1525 value = apic_read(APIC_ISR + i*0x10); 1526 for_each_set_bit(j, &value, 32) { 1527 ack_APIC_irq(); 1528 acked++; 1529 } 1530 } 1531 if (acked > 256) { 1532 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1533 break; 1534 } 1535 if (queued) { 1536 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1537 ntsc = rdtsc(); 1538 max_loops = (long long)cpu_khz << 10; 1539 max_loops -= ntsc - tsc; 1540 } else { 1541 max_loops--; 1542 } 1543 } 1544 } while (queued && max_loops > 0); 1545 WARN_ON(max_loops <= 0); 1546 } 1547 1548 /** 1549 * setup_local_APIC - setup the local APIC 1550 * 1551 * Used to setup local APIC while initializing BSP or bringing up APs. 1552 * Always called with preemption disabled. 1553 */ 1554 static void setup_local_APIC(void) 1555 { 1556 int cpu = smp_processor_id(); 1557 unsigned int value; 1558 #ifdef CONFIG_X86_32 1559 int logical_apicid, ldr_apicid; 1560 #endif 1561 1562 1563 if (disable_apic) { 1564 disable_ioapic_support(); 1565 return; 1566 } 1567 1568 #ifdef CONFIG_X86_32 1569 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1570 if (lapic_is_integrated() && apic->disable_esr) { 1571 apic_write(APIC_ESR, 0); 1572 apic_write(APIC_ESR, 0); 1573 apic_write(APIC_ESR, 0); 1574 apic_write(APIC_ESR, 0); 1575 } 1576 #endif 1577 perf_events_lapic_init(); 1578 1579 /* 1580 * Double-check whether this APIC is really registered. 1581 * This is meaningless in clustered apic mode, so we skip it. 1582 */ 1583 BUG_ON(!apic->apic_id_registered()); 1584 1585 /* 1586 * Intel recommends to set DFR, LDR and TPR before enabling 1587 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1588 * document number 292116). So here it goes... 1589 */ 1590 apic->init_apic_ldr(); 1591 1592 #ifdef CONFIG_X86_32 1593 /* 1594 * APIC LDR is initialized. If logical_apicid mapping was 1595 * initialized during get_smp_config(), make sure it matches the 1596 * actual value. 1597 */ 1598 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1599 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1600 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1601 /* always use the value from LDR */ 1602 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1603 #endif 1604 1605 /* 1606 * Set Task Priority to 'accept all'. We never change this 1607 * later on. 1608 */ 1609 value = apic_read(APIC_TASKPRI); 1610 value &= ~APIC_TPRI_MASK; 1611 apic_write(APIC_TASKPRI, value); 1612 1613 apic_pending_intr_clear(); 1614 1615 /* 1616 * Now that we are all set up, enable the APIC 1617 */ 1618 value = apic_read(APIC_SPIV); 1619 value &= ~APIC_VECTOR_MASK; 1620 /* 1621 * Enable APIC 1622 */ 1623 value |= APIC_SPIV_APIC_ENABLED; 1624 1625 #ifdef CONFIG_X86_32 1626 /* 1627 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1628 * certain networking cards. If high frequency interrupts are 1629 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1630 * entry is masked/unmasked at a high rate as well then sooner or 1631 * later IOAPIC line gets 'stuck', no more interrupts are received 1632 * from the device. If focus CPU is disabled then the hang goes 1633 * away, oh well :-( 1634 * 1635 * [ This bug can be reproduced easily with a level-triggered 1636 * PCI Ne2000 networking cards and PII/PIII processors, dual 1637 * BX chipset. ] 1638 */ 1639 /* 1640 * Actually disabling the focus CPU check just makes the hang less 1641 * frequent as it makes the interrupt distributon model be more 1642 * like LRU than MRU (the short-term load is more even across CPUs). 1643 */ 1644 1645 /* 1646 * - enable focus processor (bit==0) 1647 * - 64bit mode always use processor focus 1648 * so no need to set it 1649 */ 1650 value &= ~APIC_SPIV_FOCUS_DISABLED; 1651 #endif 1652 1653 /* 1654 * Set spurious IRQ vector 1655 */ 1656 value |= SPURIOUS_APIC_VECTOR; 1657 apic_write(APIC_SPIV, value); 1658 1659 /* 1660 * Set up LVT0, LVT1: 1661 * 1662 * set up through-local-APIC on the boot CPU's LINT0. This is not 1663 * strictly necessary in pure symmetric-IO mode, but sometimes 1664 * we delegate interrupts to the 8259A. 1665 */ 1666 /* 1667 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1668 */ 1669 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1670 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1671 value = APIC_DM_EXTINT; 1672 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1673 } else { 1674 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1675 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1676 } 1677 apic_write(APIC_LVT0, value); 1678 1679 /* 1680 * Only the BSP sees the LINT1 NMI signal by default. This can be 1681 * modified by apic_extnmi= boot option. 1682 */ 1683 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1684 apic_extnmi == APIC_EXTNMI_ALL) 1685 value = APIC_DM_NMI; 1686 else 1687 value = APIC_DM_NMI | APIC_LVT_MASKED; 1688 1689 /* Is 82489DX ? */ 1690 if (!lapic_is_integrated()) 1691 value |= APIC_LVT_LEVEL_TRIGGER; 1692 apic_write(APIC_LVT1, value); 1693 1694 #ifdef CONFIG_X86_MCE_INTEL 1695 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1696 if (!cpu) 1697 cmci_recheck(); 1698 #endif 1699 } 1700 1701 static void end_local_APIC_setup(void) 1702 { 1703 lapic_setup_esr(); 1704 1705 #ifdef CONFIG_X86_32 1706 { 1707 unsigned int value; 1708 /* Disable the local apic timer */ 1709 value = apic_read(APIC_LVTT); 1710 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1711 apic_write(APIC_LVTT, value); 1712 } 1713 #endif 1714 1715 apic_pm_activate(); 1716 } 1717 1718 /* 1719 * APIC setup function for application processors. Called from smpboot.c 1720 */ 1721 void apic_ap_setup(void) 1722 { 1723 setup_local_APIC(); 1724 end_local_APIC_setup(); 1725 } 1726 1727 #ifdef CONFIG_X86_X2APIC 1728 int x2apic_mode; 1729 1730 enum { 1731 X2APIC_OFF, 1732 X2APIC_ON, 1733 X2APIC_DISABLED, 1734 }; 1735 static int x2apic_state; 1736 1737 static void __x2apic_disable(void) 1738 { 1739 u64 msr; 1740 1741 if (!boot_cpu_has(X86_FEATURE_APIC)) 1742 return; 1743 1744 rdmsrl(MSR_IA32_APICBASE, msr); 1745 if (!(msr & X2APIC_ENABLE)) 1746 return; 1747 /* Disable xapic and x2apic first and then reenable xapic mode */ 1748 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1749 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1750 printk_once(KERN_INFO "x2apic disabled\n"); 1751 } 1752 1753 static void __x2apic_enable(void) 1754 { 1755 u64 msr; 1756 1757 rdmsrl(MSR_IA32_APICBASE, msr); 1758 if (msr & X2APIC_ENABLE) 1759 return; 1760 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1761 printk_once(KERN_INFO "x2apic enabled\n"); 1762 } 1763 1764 static int __init setup_nox2apic(char *str) 1765 { 1766 if (x2apic_enabled()) { 1767 int apicid = native_apic_msr_read(APIC_ID); 1768 1769 if (apicid >= 255) { 1770 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1771 apicid); 1772 return 0; 1773 } 1774 pr_warning("x2apic already enabled.\n"); 1775 __x2apic_disable(); 1776 } 1777 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1778 x2apic_state = X2APIC_DISABLED; 1779 x2apic_mode = 0; 1780 return 0; 1781 } 1782 early_param("nox2apic", setup_nox2apic); 1783 1784 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1785 void x2apic_setup(void) 1786 { 1787 /* 1788 * If x2apic is not in ON state, disable it if already enabled 1789 * from BIOS. 1790 */ 1791 if (x2apic_state != X2APIC_ON) { 1792 __x2apic_disable(); 1793 return; 1794 } 1795 __x2apic_enable(); 1796 } 1797 1798 static __init void x2apic_disable(void) 1799 { 1800 u32 x2apic_id, state = x2apic_state; 1801 1802 x2apic_mode = 0; 1803 x2apic_state = X2APIC_DISABLED; 1804 1805 if (state != X2APIC_ON) 1806 return; 1807 1808 x2apic_id = read_apic_id(); 1809 if (x2apic_id >= 255) 1810 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1811 1812 __x2apic_disable(); 1813 register_lapic_address(mp_lapic_addr); 1814 } 1815 1816 static __init void x2apic_enable(void) 1817 { 1818 if (x2apic_state != X2APIC_OFF) 1819 return; 1820 1821 x2apic_mode = 1; 1822 x2apic_state = X2APIC_ON; 1823 __x2apic_enable(); 1824 } 1825 1826 static __init void try_to_enable_x2apic(int remap_mode) 1827 { 1828 if (x2apic_state == X2APIC_DISABLED) 1829 return; 1830 1831 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1832 /* IR is required if there is APIC ID > 255 even when running 1833 * under KVM 1834 */ 1835 if (max_physical_apicid > 255 || 1836 !x86_init.hyper.x2apic_available()) { 1837 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1838 x2apic_disable(); 1839 return; 1840 } 1841 1842 /* 1843 * without IR all CPUs can be addressed by IOAPIC/MSI 1844 * only in physical mode 1845 */ 1846 x2apic_phys = 1; 1847 } 1848 x2apic_enable(); 1849 } 1850 1851 void __init check_x2apic(void) 1852 { 1853 if (x2apic_enabled()) { 1854 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1855 x2apic_mode = 1; 1856 x2apic_state = X2APIC_ON; 1857 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1858 x2apic_state = X2APIC_DISABLED; 1859 } 1860 } 1861 #else /* CONFIG_X86_X2APIC */ 1862 static int __init validate_x2apic(void) 1863 { 1864 if (!apic_is_x2apic_enabled()) 1865 return 0; 1866 /* 1867 * Checkme: Can we simply turn off x2apic here instead of panic? 1868 */ 1869 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1870 } 1871 early_initcall(validate_x2apic); 1872 1873 static inline void try_to_enable_x2apic(int remap_mode) { } 1874 static inline void __x2apic_enable(void) { } 1875 #endif /* !CONFIG_X86_X2APIC */ 1876 1877 void __init enable_IR_x2apic(void) 1878 { 1879 unsigned long flags; 1880 int ret, ir_stat; 1881 1882 if (skip_ioapic_setup) { 1883 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1884 return; 1885 } 1886 1887 ir_stat = irq_remapping_prepare(); 1888 if (ir_stat < 0 && !x2apic_supported()) 1889 return; 1890 1891 ret = save_ioapic_entries(); 1892 if (ret) { 1893 pr_info("Saving IO-APIC state failed: %d\n", ret); 1894 return; 1895 } 1896 1897 local_irq_save(flags); 1898 legacy_pic->mask_all(); 1899 mask_ioapic_entries(); 1900 1901 /* If irq_remapping_prepare() succeeded, try to enable it */ 1902 if (ir_stat >= 0) 1903 ir_stat = irq_remapping_enable(); 1904 /* ir_stat contains the remap mode or an error code */ 1905 try_to_enable_x2apic(ir_stat); 1906 1907 if (ir_stat < 0) 1908 restore_ioapic_entries(); 1909 legacy_pic->restore_mask(); 1910 local_irq_restore(flags); 1911 } 1912 1913 #ifdef CONFIG_X86_64 1914 /* 1915 * Detect and enable local APICs on non-SMP boards. 1916 * Original code written by Keir Fraser. 1917 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1918 * not correctly set up (usually the APIC timer won't work etc.) 1919 */ 1920 static int __init detect_init_APIC(void) 1921 { 1922 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1923 pr_info("No local APIC present\n"); 1924 return -1; 1925 } 1926 1927 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1928 return 0; 1929 } 1930 #else 1931 1932 static int __init apic_verify(void) 1933 { 1934 u32 features, h, l; 1935 1936 /* 1937 * The APIC feature bit should now be enabled 1938 * in `cpuid' 1939 */ 1940 features = cpuid_edx(1); 1941 if (!(features & (1 << X86_FEATURE_APIC))) { 1942 pr_warning("Could not enable APIC!\n"); 1943 return -1; 1944 } 1945 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1946 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1947 1948 /* The BIOS may have set up the APIC at some other address */ 1949 if (boot_cpu_data.x86 >= 6) { 1950 rdmsr(MSR_IA32_APICBASE, l, h); 1951 if (l & MSR_IA32_APICBASE_ENABLE) 1952 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1953 } 1954 1955 pr_info("Found and enabled local APIC!\n"); 1956 return 0; 1957 } 1958 1959 int __init apic_force_enable(unsigned long addr) 1960 { 1961 u32 h, l; 1962 1963 if (disable_apic) 1964 return -1; 1965 1966 /* 1967 * Some BIOSes disable the local APIC in the APIC_BASE 1968 * MSR. This can only be done in software for Intel P6 or later 1969 * and AMD K7 (Model > 1) or later. 1970 */ 1971 if (boot_cpu_data.x86 >= 6) { 1972 rdmsr(MSR_IA32_APICBASE, l, h); 1973 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1974 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1975 l &= ~MSR_IA32_APICBASE_BASE; 1976 l |= MSR_IA32_APICBASE_ENABLE | addr; 1977 wrmsr(MSR_IA32_APICBASE, l, h); 1978 enabled_via_apicbase = 1; 1979 } 1980 } 1981 return apic_verify(); 1982 } 1983 1984 /* 1985 * Detect and initialize APIC 1986 */ 1987 static int __init detect_init_APIC(void) 1988 { 1989 /* Disabled by kernel option? */ 1990 if (disable_apic) 1991 return -1; 1992 1993 switch (boot_cpu_data.x86_vendor) { 1994 case X86_VENDOR_AMD: 1995 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1996 (boot_cpu_data.x86 >= 15)) 1997 break; 1998 goto no_apic; 1999 case X86_VENDOR_HYGON: 2000 break; 2001 case X86_VENDOR_INTEL: 2002 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 2003 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2004 break; 2005 goto no_apic; 2006 default: 2007 goto no_apic; 2008 } 2009 2010 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2011 /* 2012 * Over-ride BIOS and try to enable the local APIC only if 2013 * "lapic" specified. 2014 */ 2015 if (!force_enable_local_apic) { 2016 pr_info("Local APIC disabled by BIOS -- " 2017 "you can enable it with \"lapic\"\n"); 2018 return -1; 2019 } 2020 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 2021 return -1; 2022 } else { 2023 if (apic_verify()) 2024 return -1; 2025 } 2026 2027 apic_pm_activate(); 2028 2029 return 0; 2030 2031 no_apic: 2032 pr_info("No local APIC present or hardware disabled\n"); 2033 return -1; 2034 } 2035 #endif 2036 2037 /** 2038 * init_apic_mappings - initialize APIC mappings 2039 */ 2040 void __init init_apic_mappings(void) 2041 { 2042 unsigned int new_apicid; 2043 2044 apic_check_deadline_errata(); 2045 2046 if (x2apic_mode) { 2047 boot_cpu_physical_apicid = read_apic_id(); 2048 return; 2049 } 2050 2051 /* If no local APIC can be found return early */ 2052 if (!smp_found_config && detect_init_APIC()) { 2053 /* lets NOP'ify apic operations */ 2054 pr_info("APIC: disable apic facility\n"); 2055 apic_disable(); 2056 } else { 2057 apic_phys = mp_lapic_addr; 2058 2059 /* 2060 * If the system has ACPI MADT tables or MP info, the LAPIC 2061 * address is already registered. 2062 */ 2063 if (!acpi_lapic && !smp_found_config) 2064 register_lapic_address(apic_phys); 2065 } 2066 2067 /* 2068 * Fetch the APIC ID of the BSP in case we have a 2069 * default configuration (or the MP table is broken). 2070 */ 2071 new_apicid = read_apic_id(); 2072 if (boot_cpu_physical_apicid != new_apicid) { 2073 boot_cpu_physical_apicid = new_apicid; 2074 /* 2075 * yeah -- we lie about apic_version 2076 * in case if apic was disabled via boot option 2077 * but it's not a problem for SMP compiled kernel 2078 * since apic_intr_mode_select is prepared for such 2079 * a case and disable smp mode 2080 */ 2081 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2082 } 2083 } 2084 2085 void __init register_lapic_address(unsigned long address) 2086 { 2087 mp_lapic_addr = address; 2088 2089 if (!x2apic_mode) { 2090 set_fixmap_nocache(FIX_APIC_BASE, address); 2091 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2092 APIC_BASE, address); 2093 } 2094 if (boot_cpu_physical_apicid == -1U) { 2095 boot_cpu_physical_apicid = read_apic_id(); 2096 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2097 } 2098 } 2099 2100 /* 2101 * Local APIC interrupts 2102 */ 2103 2104 /* 2105 * This interrupt should _never_ happen with our APIC/SMP architecture 2106 */ 2107 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2108 { 2109 u8 vector = ~regs->orig_ax; 2110 u32 v; 2111 2112 entering_irq(); 2113 trace_spurious_apic_entry(vector); 2114 2115 inc_irq_stat(irq_spurious_count); 2116 2117 /* 2118 * If this is a spurious interrupt then do not acknowledge 2119 */ 2120 if (vector == SPURIOUS_APIC_VECTOR) { 2121 /* See SDM vol 3 */ 2122 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2123 smp_processor_id()); 2124 goto out; 2125 } 2126 2127 /* 2128 * If it is a vectored one, verify it's set in the ISR. If set, 2129 * acknowledge it. 2130 */ 2131 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2132 if (v & (1 << (vector & 0x1f))) { 2133 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2134 vector, smp_processor_id()); 2135 ack_APIC_irq(); 2136 } else { 2137 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2138 vector, smp_processor_id()); 2139 } 2140 out: 2141 trace_spurious_apic_exit(vector); 2142 exiting_irq(); 2143 } 2144 2145 /* 2146 * This interrupt should never happen with our APIC/SMP architecture 2147 */ 2148 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2149 { 2150 static const char * const error_interrupt_reason[] = { 2151 "Send CS error", /* APIC Error Bit 0 */ 2152 "Receive CS error", /* APIC Error Bit 1 */ 2153 "Send accept error", /* APIC Error Bit 2 */ 2154 "Receive accept error", /* APIC Error Bit 3 */ 2155 "Redirectable IPI", /* APIC Error Bit 4 */ 2156 "Send illegal vector", /* APIC Error Bit 5 */ 2157 "Received illegal vector", /* APIC Error Bit 6 */ 2158 "Illegal register address", /* APIC Error Bit 7 */ 2159 }; 2160 u32 v, i = 0; 2161 2162 entering_irq(); 2163 trace_error_apic_entry(ERROR_APIC_VECTOR); 2164 2165 /* First tickle the hardware, only then report what went on. -- REW */ 2166 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2167 apic_write(APIC_ESR, 0); 2168 v = apic_read(APIC_ESR); 2169 ack_APIC_irq(); 2170 atomic_inc(&irq_err_count); 2171 2172 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2173 smp_processor_id(), v); 2174 2175 v &= 0xff; 2176 while (v) { 2177 if (v & 0x1) 2178 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2179 i++; 2180 v >>= 1; 2181 } 2182 2183 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2184 2185 trace_error_apic_exit(ERROR_APIC_VECTOR); 2186 exiting_irq(); 2187 } 2188 2189 /** 2190 * connect_bsp_APIC - attach the APIC to the interrupt system 2191 */ 2192 static void __init connect_bsp_APIC(void) 2193 { 2194 #ifdef CONFIG_X86_32 2195 if (pic_mode) { 2196 /* 2197 * Do not trust the local APIC being empty at bootup. 2198 */ 2199 clear_local_APIC(); 2200 /* 2201 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2202 * local APIC to INT and NMI lines. 2203 */ 2204 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2205 "enabling APIC mode.\n"); 2206 imcr_pic_to_apic(); 2207 } 2208 #endif 2209 } 2210 2211 /** 2212 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2213 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2214 * 2215 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2216 * APIC is disabled. 2217 */ 2218 void disconnect_bsp_APIC(int virt_wire_setup) 2219 { 2220 unsigned int value; 2221 2222 #ifdef CONFIG_X86_32 2223 if (pic_mode) { 2224 /* 2225 * Put the board back into PIC mode (has an effect only on 2226 * certain older boards). Note that APIC interrupts, including 2227 * IPIs, won't work beyond this point! The only exception are 2228 * INIT IPIs. 2229 */ 2230 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2231 "entering PIC mode.\n"); 2232 imcr_apic_to_pic(); 2233 return; 2234 } 2235 #endif 2236 2237 /* Go back to Virtual Wire compatibility mode */ 2238 2239 /* For the spurious interrupt use vector F, and enable it */ 2240 value = apic_read(APIC_SPIV); 2241 value &= ~APIC_VECTOR_MASK; 2242 value |= APIC_SPIV_APIC_ENABLED; 2243 value |= 0xf; 2244 apic_write(APIC_SPIV, value); 2245 2246 if (!virt_wire_setup) { 2247 /* 2248 * For LVT0 make it edge triggered, active high, 2249 * external and enabled 2250 */ 2251 value = apic_read(APIC_LVT0); 2252 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2253 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2254 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2255 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2256 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2257 apic_write(APIC_LVT0, value); 2258 } else { 2259 /* Disable LVT0 */ 2260 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2261 } 2262 2263 /* 2264 * For LVT1 make it edge triggered, active high, 2265 * nmi and enabled 2266 */ 2267 value = apic_read(APIC_LVT1); 2268 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2269 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2270 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2271 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2272 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2273 apic_write(APIC_LVT1, value); 2274 } 2275 2276 /* 2277 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2278 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2279 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2280 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2281 * 2282 * NOTE: Reserve 0 for BSP. 2283 */ 2284 static int nr_logical_cpuids = 1; 2285 2286 /* 2287 * Used to store mapping between logical CPU IDs and APIC IDs. 2288 */ 2289 static int cpuid_to_apicid[] = { 2290 [0 ... NR_CPUS - 1] = -1, 2291 }; 2292 2293 #ifdef CONFIG_SMP 2294 /** 2295 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2296 * @id: APIC ID to check 2297 */ 2298 bool apic_id_is_primary_thread(unsigned int apicid) 2299 { 2300 u32 mask; 2301 2302 if (smp_num_siblings == 1) 2303 return true; 2304 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2305 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2306 return !(apicid & mask); 2307 } 2308 #endif 2309 2310 /* 2311 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2312 * and cpuid_to_apicid[] synchronized. 2313 */ 2314 static int allocate_logical_cpuid(int apicid) 2315 { 2316 int i; 2317 2318 /* 2319 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2320 * check if the kernel has allocated a cpuid for it. 2321 */ 2322 for (i = 0; i < nr_logical_cpuids; i++) { 2323 if (cpuid_to_apicid[i] == apicid) 2324 return i; 2325 } 2326 2327 /* Allocate a new cpuid. */ 2328 if (nr_logical_cpuids >= nr_cpu_ids) { 2329 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2330 "Processor %d/0x%x and the rest are ignored.\n", 2331 nr_cpu_ids, nr_logical_cpuids, apicid); 2332 return -EINVAL; 2333 } 2334 2335 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2336 return nr_logical_cpuids++; 2337 } 2338 2339 int generic_processor_info(int apicid, int version) 2340 { 2341 int cpu, max = nr_cpu_ids; 2342 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2343 phys_cpu_present_map); 2344 2345 /* 2346 * boot_cpu_physical_apicid is designed to have the apicid 2347 * returned by read_apic_id(), i.e, the apicid of the 2348 * currently booting-up processor. However, on some platforms, 2349 * it is temporarily modified by the apicid reported as BSP 2350 * through MP table. Concretely: 2351 * 2352 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2353 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2354 * 2355 * This function is executed with the modified 2356 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2357 * parameter doesn't work to disable APs on kdump 2nd kernel. 2358 * 2359 * Since fixing handling of boot_cpu_physical_apicid requires 2360 * another discussion and tests on each platform, we leave it 2361 * for now and here we use read_apic_id() directly in this 2362 * function, generic_processor_info(). 2363 */ 2364 if (disabled_cpu_apicid != BAD_APICID && 2365 disabled_cpu_apicid != read_apic_id() && 2366 disabled_cpu_apicid == apicid) { 2367 int thiscpu = num_processors + disabled_cpus; 2368 2369 pr_warning("APIC: Disabling requested cpu." 2370 " Processor %d/0x%x ignored.\n", 2371 thiscpu, apicid); 2372 2373 disabled_cpus++; 2374 return -ENODEV; 2375 } 2376 2377 /* 2378 * If boot cpu has not been detected yet, then only allow upto 2379 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2380 */ 2381 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2382 apicid != boot_cpu_physical_apicid) { 2383 int thiscpu = max + disabled_cpus - 1; 2384 2385 pr_warning( 2386 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2387 " reached. Keeping one slot for boot cpu." 2388 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2389 2390 disabled_cpus++; 2391 return -ENODEV; 2392 } 2393 2394 if (num_processors >= nr_cpu_ids) { 2395 int thiscpu = max + disabled_cpus; 2396 2397 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2398 "reached. Processor %d/0x%x ignored.\n", 2399 max, thiscpu, apicid); 2400 2401 disabled_cpus++; 2402 return -EINVAL; 2403 } 2404 2405 if (apicid == boot_cpu_physical_apicid) { 2406 /* 2407 * x86_bios_cpu_apicid is required to have processors listed 2408 * in same order as logical cpu numbers. Hence the first 2409 * entry is BSP, and so on. 2410 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2411 * for BSP. 2412 */ 2413 cpu = 0; 2414 2415 /* Logical cpuid 0 is reserved for BSP. */ 2416 cpuid_to_apicid[0] = apicid; 2417 } else { 2418 cpu = allocate_logical_cpuid(apicid); 2419 if (cpu < 0) { 2420 disabled_cpus++; 2421 return -EINVAL; 2422 } 2423 } 2424 2425 /* 2426 * Validate version 2427 */ 2428 if (version == 0x0) { 2429 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2430 cpu, apicid); 2431 version = 0x10; 2432 } 2433 2434 if (version != boot_cpu_apic_version) { 2435 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2436 boot_cpu_apic_version, cpu, version); 2437 } 2438 2439 if (apicid > max_physical_apicid) 2440 max_physical_apicid = apicid; 2441 2442 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2443 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2444 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2445 #endif 2446 #ifdef CONFIG_X86_32 2447 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2448 apic->x86_32_early_logical_apicid(cpu); 2449 #endif 2450 set_cpu_possible(cpu, true); 2451 physid_set(apicid, phys_cpu_present_map); 2452 set_cpu_present(cpu, true); 2453 num_processors++; 2454 2455 return cpu; 2456 } 2457 2458 int hard_smp_processor_id(void) 2459 { 2460 return read_apic_id(); 2461 } 2462 2463 /* 2464 * Override the generic EOI implementation with an optimized version. 2465 * Only called during early boot when only one CPU is active and with 2466 * interrupts disabled, so we know this does not race with actual APIC driver 2467 * use. 2468 */ 2469 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2470 { 2471 struct apic **drv; 2472 2473 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2474 /* Should happen once for each apic */ 2475 WARN_ON((*drv)->eoi_write == eoi_write); 2476 (*drv)->native_eoi_write = (*drv)->eoi_write; 2477 (*drv)->eoi_write = eoi_write; 2478 } 2479 } 2480 2481 static void __init apic_bsp_up_setup(void) 2482 { 2483 #ifdef CONFIG_X86_64 2484 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2485 #else 2486 /* 2487 * Hack: In case of kdump, after a crash, kernel might be booting 2488 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2489 * might be zero if read from MP tables. Get it from LAPIC. 2490 */ 2491 # ifdef CONFIG_CRASH_DUMP 2492 boot_cpu_physical_apicid = read_apic_id(); 2493 # endif 2494 #endif 2495 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2496 } 2497 2498 /** 2499 * apic_bsp_setup - Setup function for local apic and io-apic 2500 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2501 */ 2502 static void __init apic_bsp_setup(bool upmode) 2503 { 2504 connect_bsp_APIC(); 2505 if (upmode) 2506 apic_bsp_up_setup(); 2507 setup_local_APIC(); 2508 2509 enable_IO_APIC(); 2510 end_local_APIC_setup(); 2511 irq_remap_enable_fault_handling(); 2512 setup_IO_APIC(); 2513 } 2514 2515 #ifdef CONFIG_UP_LATE_INIT 2516 void __init up_late_init(void) 2517 { 2518 if (apic_intr_mode == APIC_PIC) 2519 return; 2520 2521 /* Setup local timer */ 2522 x86_init.timers.setup_percpu_clockev(); 2523 } 2524 #endif 2525 2526 /* 2527 * Power management 2528 */ 2529 #ifdef CONFIG_PM 2530 2531 static struct { 2532 /* 2533 * 'active' is true if the local APIC was enabled by us and 2534 * not the BIOS; this signifies that we are also responsible 2535 * for disabling it before entering apm/acpi suspend 2536 */ 2537 int active; 2538 /* r/w apic fields */ 2539 unsigned int apic_id; 2540 unsigned int apic_taskpri; 2541 unsigned int apic_ldr; 2542 unsigned int apic_dfr; 2543 unsigned int apic_spiv; 2544 unsigned int apic_lvtt; 2545 unsigned int apic_lvtpc; 2546 unsigned int apic_lvt0; 2547 unsigned int apic_lvt1; 2548 unsigned int apic_lvterr; 2549 unsigned int apic_tmict; 2550 unsigned int apic_tdcr; 2551 unsigned int apic_thmr; 2552 unsigned int apic_cmci; 2553 } apic_pm_state; 2554 2555 static int lapic_suspend(void) 2556 { 2557 unsigned long flags; 2558 int maxlvt; 2559 2560 if (!apic_pm_state.active) 2561 return 0; 2562 2563 maxlvt = lapic_get_maxlvt(); 2564 2565 apic_pm_state.apic_id = apic_read(APIC_ID); 2566 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2567 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2568 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2569 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2570 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2571 if (maxlvt >= 4) 2572 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2573 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2574 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2575 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2576 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2577 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2578 #ifdef CONFIG_X86_THERMAL_VECTOR 2579 if (maxlvt >= 5) 2580 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2581 #endif 2582 #ifdef CONFIG_X86_MCE_INTEL 2583 if (maxlvt >= 6) 2584 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2585 #endif 2586 2587 local_irq_save(flags); 2588 disable_local_APIC(); 2589 2590 irq_remapping_disable(); 2591 2592 local_irq_restore(flags); 2593 return 0; 2594 } 2595 2596 static void lapic_resume(void) 2597 { 2598 unsigned int l, h; 2599 unsigned long flags; 2600 int maxlvt; 2601 2602 if (!apic_pm_state.active) 2603 return; 2604 2605 local_irq_save(flags); 2606 2607 /* 2608 * IO-APIC and PIC have their own resume routines. 2609 * We just mask them here to make sure the interrupt 2610 * subsystem is completely quiet while we enable x2apic 2611 * and interrupt-remapping. 2612 */ 2613 mask_ioapic_entries(); 2614 legacy_pic->mask_all(); 2615 2616 if (x2apic_mode) { 2617 __x2apic_enable(); 2618 } else { 2619 /* 2620 * Make sure the APICBASE points to the right address 2621 * 2622 * FIXME! This will be wrong if we ever support suspend on 2623 * SMP! We'll need to do this as part of the CPU restore! 2624 */ 2625 if (boot_cpu_data.x86 >= 6) { 2626 rdmsr(MSR_IA32_APICBASE, l, h); 2627 l &= ~MSR_IA32_APICBASE_BASE; 2628 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2629 wrmsr(MSR_IA32_APICBASE, l, h); 2630 } 2631 } 2632 2633 maxlvt = lapic_get_maxlvt(); 2634 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2635 apic_write(APIC_ID, apic_pm_state.apic_id); 2636 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2637 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2638 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2639 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2640 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2641 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2642 #ifdef CONFIG_X86_THERMAL_VECTOR 2643 if (maxlvt >= 5) 2644 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2645 #endif 2646 #ifdef CONFIG_X86_MCE_INTEL 2647 if (maxlvt >= 6) 2648 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2649 #endif 2650 if (maxlvt >= 4) 2651 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2652 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2653 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2654 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2655 apic_write(APIC_ESR, 0); 2656 apic_read(APIC_ESR); 2657 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2658 apic_write(APIC_ESR, 0); 2659 apic_read(APIC_ESR); 2660 2661 irq_remapping_reenable(x2apic_mode); 2662 2663 local_irq_restore(flags); 2664 } 2665 2666 /* 2667 * This device has no shutdown method - fully functioning local APICs 2668 * are needed on every CPU up until machine_halt/restart/poweroff. 2669 */ 2670 2671 static struct syscore_ops lapic_syscore_ops = { 2672 .resume = lapic_resume, 2673 .suspend = lapic_suspend, 2674 }; 2675 2676 static void apic_pm_activate(void) 2677 { 2678 apic_pm_state.active = 1; 2679 } 2680 2681 static int __init init_lapic_sysfs(void) 2682 { 2683 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2684 if (boot_cpu_has(X86_FEATURE_APIC)) 2685 register_syscore_ops(&lapic_syscore_ops); 2686 2687 return 0; 2688 } 2689 2690 /* local apic needs to resume before other devices access its registers. */ 2691 core_initcall(init_lapic_sysfs); 2692 2693 #else /* CONFIG_PM */ 2694 2695 static void apic_pm_activate(void) { } 2696 2697 #endif /* CONFIG_PM */ 2698 2699 #ifdef CONFIG_X86_64 2700 2701 static int multi_checked; 2702 static int multi; 2703 2704 static int set_multi(const struct dmi_system_id *d) 2705 { 2706 if (multi) 2707 return 0; 2708 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2709 multi = 1; 2710 return 0; 2711 } 2712 2713 static const struct dmi_system_id multi_dmi_table[] = { 2714 { 2715 .callback = set_multi, 2716 .ident = "IBM System Summit2", 2717 .matches = { 2718 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2719 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2720 }, 2721 }, 2722 {} 2723 }; 2724 2725 static void dmi_check_multi(void) 2726 { 2727 if (multi_checked) 2728 return; 2729 2730 dmi_check_system(multi_dmi_table); 2731 multi_checked = 1; 2732 } 2733 2734 /* 2735 * apic_is_clustered_box() -- Check if we can expect good TSC 2736 * 2737 * Thus far, the major user of this is IBM's Summit2 series: 2738 * Clustered boxes may have unsynced TSC problems if they are 2739 * multi-chassis. 2740 * Use DMI to check them 2741 */ 2742 int apic_is_clustered_box(void) 2743 { 2744 dmi_check_multi(); 2745 return multi; 2746 } 2747 #endif 2748 2749 /* 2750 * APIC command line parameters 2751 */ 2752 static int __init setup_disableapic(char *arg) 2753 { 2754 disable_apic = 1; 2755 setup_clear_cpu_cap(X86_FEATURE_APIC); 2756 return 0; 2757 } 2758 early_param("disableapic", setup_disableapic); 2759 2760 /* same as disableapic, for compatibility */ 2761 static int __init setup_nolapic(char *arg) 2762 { 2763 return setup_disableapic(arg); 2764 } 2765 early_param("nolapic", setup_nolapic); 2766 2767 static int __init parse_lapic_timer_c2_ok(char *arg) 2768 { 2769 local_apic_timer_c2_ok = 1; 2770 return 0; 2771 } 2772 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2773 2774 static int __init parse_disable_apic_timer(char *arg) 2775 { 2776 disable_apic_timer = 1; 2777 return 0; 2778 } 2779 early_param("noapictimer", parse_disable_apic_timer); 2780 2781 static int __init parse_nolapic_timer(char *arg) 2782 { 2783 disable_apic_timer = 1; 2784 return 0; 2785 } 2786 early_param("nolapic_timer", parse_nolapic_timer); 2787 2788 static int __init apic_set_verbosity(char *arg) 2789 { 2790 if (!arg) { 2791 #ifdef CONFIG_X86_64 2792 skip_ioapic_setup = 0; 2793 return 0; 2794 #endif 2795 return -EINVAL; 2796 } 2797 2798 if (strcmp("debug", arg) == 0) 2799 apic_verbosity = APIC_DEBUG; 2800 else if (strcmp("verbose", arg) == 0) 2801 apic_verbosity = APIC_VERBOSE; 2802 #ifdef CONFIG_X86_64 2803 else { 2804 pr_warning("APIC Verbosity level %s not recognised" 2805 " use apic=verbose or apic=debug\n", arg); 2806 return -EINVAL; 2807 } 2808 #endif 2809 2810 return 0; 2811 } 2812 early_param("apic", apic_set_verbosity); 2813 2814 static int __init lapic_insert_resource(void) 2815 { 2816 if (!apic_phys) 2817 return -1; 2818 2819 /* Put local APIC into the resource map. */ 2820 lapic_resource.start = apic_phys; 2821 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2822 insert_resource(&iomem_resource, &lapic_resource); 2823 2824 return 0; 2825 } 2826 2827 /* 2828 * need call insert after e820__reserve_resources() 2829 * that is using request_resource 2830 */ 2831 late_initcall(lapic_insert_resource); 2832 2833 static int __init apic_set_disabled_cpu_apicid(char *arg) 2834 { 2835 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2836 return -EINVAL; 2837 2838 return 0; 2839 } 2840 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2841 2842 static int __init apic_set_extnmi(char *arg) 2843 { 2844 if (!arg) 2845 return -EINVAL; 2846 2847 if (!strncmp("all", arg, 3)) 2848 apic_extnmi = APIC_EXTNMI_ALL; 2849 else if (!strncmp("none", arg, 4)) 2850 apic_extnmi = APIC_EXTNMI_NONE; 2851 else if (!strncmp("bsp", arg, 3)) 2852 apic_extnmi = APIC_EXTNMI_BSP; 2853 else { 2854 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2855 return -EINVAL; 2856 } 2857 2858 return 0; 2859 } 2860 early_param("apic_extnmi", apic_set_extnmi); 2861