arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes

[ Upstream commit 833948fb2b63155847ab691a54800f801555429b ]

The RZ/G2L(C) SoC is equipped with the GIC-600. The GICD is 64KiB +
64KiB fo

arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes

[ Upstream commit 833948fb2b63155847ab691a54800f801555429b ]

The RZ/G2L(C) SoC is equipped with the GIC-600. The GICD is 64KiB +
64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per
CPU.

Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQ

[ Upstream commit ecbc5206a1a0532258144a4703cccf4e70f3fe6c ]

Add the missing fifth interrupt to the device node that represe

arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQ

[ Upstream commit ecbc5206a1a0532258144a4703cccf4e70f3fe6c ]

Add the missing fifth interrupt to the device node that represents the
ARM architected timer. While at it, add an interrupt-names property for
clarity,

Fixes: 68a45525297b2e9a ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/21f556eb7e903d5b9f4c96188fd4b6ae0db71856.1718890849.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes

[ Upstream commit 14fe225dd5fcd5928583b0bcc34398a581f51602 ]

The IRQC IP block supports Bus error and ECCRAM interrupts on RZ/G2L an

arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes

[ Upstream commit 14fe225dd5fcd5928583b0bcc34398a581f51602 ]

The IRQC IP block supports Bus error and ECCRAM interrupts on RZ/G2L and
alike SoC's (listed below). Update the IRQC nodes with the missing
interrupts, and additionally, include the 'interrupt-names' properties
in the IRQC nodes so that the driver can parse interrupts by name.

- R9A07G043U - RZ/G2UL
- R9A07G044L/R9A07G044LC - RZ/{G2L,G2LC}
- R9A07G054 - RZ/V2L

Fixes: 5edc51af5b30 ("arm64: dts: renesas: r9a07g044: Add IRQC node")
Fixes: 48ab6eddd8bb ("arm64: dts: renesas: r9a07g043u: Add IRQC node")
Fixes: 379478ab09e0 ("arm64: dts: renesas: r9a07g054: Add IRQC node")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240205144421.51195-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels

As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow
interrupt names start with 'tci' instead of 'tg

arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels

As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow
interrupt names start with 'tci' instead of 'tgi'.

Replace the below overflow/underflow interrupt names:
- tgiv0->tciv0
- tgiv1->tciv1
- tgiu1->tciu1
- tgiv2->tciv2
- tgiu2->tciu2
- tgiv3->tciv3
- tgiv4->tciv4
- tgiv6->tciv6
- tgiv7->tciv7
- tgiv8->tciv8
- tgiu8->tciu8

Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node")
Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230724091927.123847-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add MTU3a node

Add MTU3a node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@gli

arm64: dts: renesas: r9a07g044: Add MTU3a node

Add MTU3a node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230417090159.191346-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add DSI node

Add DSI node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: ht

arm64: dts: renesas: r9a07g044: Add DSI node

Add DSI node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add vspd node

Add vspd node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link:

arm64: dts: renesas: r9a07g044: Add vspd node

Add vspd node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add fcpvd node

Add fcpvd node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link

arm64: dts: renesas: r9a07g044: Add fcpvd node

Add fcpvd node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes

Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uy

arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes

Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes

Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.

Signed-off-by: Biju Das <biju.das.jz@bp.r

arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes

Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels

From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI
channels have been updated,

SPI 329 - SSIF0 is now marked a

arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels

From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI
channels have been updated,

SPI 329 - SSIF0 is now marked as reserved
SPI 333 - SSIF1 is now marked as reserved
SPI 335 - SSIF2 is now marked as reserved
SPI 336 - SSIF2 is now marked as reserved
SPI 341 - SSIF3 is now marked as reserved

This patch drops the above IRQs from SoC DTSI.

Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems

The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them

arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems

The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node

Enable the performance monitor unit for the Cortex-A55 cores on the
RZ/G2L (r9a07g044) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-l

arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node

Enable the performance monitor unit for the Cortex-A55 cores on the
RZ/G2L (r9a07g044) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes

This fixes the below dtbs_check warning:

arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: pinctrl@11030000: #address-cells:

arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes

This fixes the below dtbs_check warning:

arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed:
[[2]] is not of type 'object'
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed:
[[2]] is not of type 'object'
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed:
[[2]] is not of type 'object'
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

Drop #address-cells properties from pinctrl nodes as they have no
addressed child nodes.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221107172953.63218-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20221107172953.63218-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: rzg2l: Add missing cache-level properties

The DeviceTree Specification v0.3 specifies that the cache node
'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared

arm64: dts: renesas: rzg2l: Add missing cache-level properties

The DeviceTree Specification v0.3 specifies that the cache node
'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared
Cache Nodes.

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-19-pierre.gondois@arm.com
[geert: Update description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: rzg2l: Drop WDT2 nodes

On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU
would result

arm64: dts: renesas: rzg2l: Drop WDT2 nodes

On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU
would result in unexpected behaviour. Hence drop all WDT2 nodes and
their references from the affected SoC and SoM DTSI files.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: Adjust whitespace around '{'

Drop extra space around the '{' sign. No functional changes (same DTB).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link

arm64: dts: renesas: Adjust whitespace around '{'

Drop extra space around the '{' sign. No functional changes (same DTB).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220916100251.20329-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt types

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.

Signed-off-b

arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt types

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: f9a2adcc9e908907 ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes")
Link: https://lore.kernel.org/r/20220802101534.1401342-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add DMA support to RSPI

Add DMA properties to RSPI nodes to support DMA operation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org

arm64: dts: renesas: r9a07g044: Add DMA support to RSPI

Add DMA properties to RSPI nodes to support DMA operation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220728122312.189766-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts

Add required properties in pinctrl node to handle GPIO interrupts.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.

arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts

Add required properties in pinctrl node to handle GPIO interrupts.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220718195651.7711-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Add IRQC node

Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20

arm64: dts: renesas: r9a07g044: Add IRQC node

Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220718195651.7711-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Fix external clk node names

Add suffix '-clk' for can and extal clk node names and replace the
clk node names audio_clk{1,2} with audio{1,2}-clk as per the device
tre

arm64: dts: renesas: r9a07g044: Fix external clk node names

Add suffix '-clk' for can and extal clk node names and replace the
clk node names audio_clk{1,2} with audio{1,2}-clk as per the device
tree specification.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220428133156.18080-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: Fix pin controller node names

Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.

Signed-off

arm64: dts: renesas: Fix pin controller node names

Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be

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arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node

Add Mali-G31 GPU node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp

arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node

Add Mali-G31 GPU node to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA

Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supp

arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA

Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
and others for r8a77990 SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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