1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g044-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g044"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio_clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio_clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 }; 113 }; 114 115 psci { 116 compatible = "arm,psci-1.0", "arm,psci-0.2"; 117 method = "smc"; 118 }; 119 120 soc: soc { 121 compatible = "simple-bus"; 122 interrupt-parent = <&gic>; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 ssi0: ssi@10049c00 { 128 compatible = "renesas,r9a07g044-ssi", 129 "renesas,rz-ssi"; 130 reg = <0 0x10049c00 0 0x400>; 131 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 133 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 134 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 135 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 136 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, 137 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, 138 <&audio_clk1>, <&audio_clk2>; 139 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 140 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; 141 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 142 dma-names = "tx", "rx"; 143 power-domains = <&cpg>; 144 #sound-dai-cells = <0>; 145 status = "disabled"; 146 }; 147 148 ssi1: ssi@1004a000 { 149 compatible = "renesas,r9a07g044-ssi", 150 "renesas,rz-ssi"; 151 reg = <0 0x1004a000 0 0x400>; 152 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 154 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 155 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 156 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 157 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, 158 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, 159 <&audio_clk1>, <&audio_clk2>; 160 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 161 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; 162 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 163 dma-names = "tx", "rx"; 164 power-domains = <&cpg>; 165 #sound-dai-cells = <0>; 166 status = "disabled"; 167 }; 168 169 ssi2: ssi@1004a400 { 170 compatible = "renesas,r9a07g044-ssi", 171 "renesas,rz-ssi"; 172 reg = <0 0x1004a400 0 0x400>; 173 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 175 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 176 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 177 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 178 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, 179 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, 180 <&audio_clk1>, <&audio_clk2>; 181 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 182 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; 183 dmas = <&dmac 0x265f>; 184 dma-names = "rt"; 185 power-domains = <&cpg>; 186 #sound-dai-cells = <0>; 187 status = "disabled"; 188 }; 189 190 ssi3: ssi@1004a800 { 191 compatible = "renesas,r9a07g044-ssi", 192 "renesas,rz-ssi"; 193 reg = <0 0x1004a800 0 0x400>; 194 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 196 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 197 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 198 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 199 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, 200 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, 201 <&audio_clk1>, <&audio_clk2>; 202 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 203 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; 204 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 205 dma-names = "tx", "rx"; 206 power-domains = <&cpg>; 207 #sound-dai-cells = <0>; 208 status = "disabled"; 209 }; 210 211 spi0: spi@1004ac00 { 212 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 213 reg = <0 0x1004ac00 0 0x400>; 214 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 217 interrupt-names = "error", "rx", "tx"; 218 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; 219 resets = <&cpg R9A07G044_RSPI0_RST>; 220 power-domains = <&cpg>; 221 num-cs = <1>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 status = "disabled"; 225 }; 226 227 spi1: spi@1004b000 { 228 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 229 reg = <0 0x1004b000 0 0x400>; 230 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-names = "error", "rx", "tx"; 234 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; 235 resets = <&cpg R9A07G044_RSPI1_RST>; 236 power-domains = <&cpg>; 237 num-cs = <1>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 spi2: spi@1004b400 { 244 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 245 reg = <0 0x1004b400 0 0x400>; 246 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-names = "error", "rx", "tx"; 250 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; 251 resets = <&cpg R9A07G044_RSPI2_RST>; 252 power-domains = <&cpg>; 253 num-cs = <1>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 status = "disabled"; 257 }; 258 259 scif0: serial@1004b800 { 260 compatible = "renesas,scif-r9a07g044"; 261 reg = <0 0x1004b800 0 0x400>; 262 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-names = "eri", "rxi", "txi", 269 "bri", "dri", "tei"; 270 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; 271 clock-names = "fck"; 272 power-domains = <&cpg>; 273 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; 274 status = "disabled"; 275 }; 276 277 scif1: serial@1004bc00 { 278 compatible = "renesas,scif-r9a07g044"; 279 reg = <0 0x1004bc00 0 0x400>; 280 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-names = "eri", "rxi", "txi", 287 "bri", "dri", "tei"; 288 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; 289 clock-names = "fck"; 290 power-domains = <&cpg>; 291 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; 292 status = "disabled"; 293 }; 294 295 scif2: serial@1004c000 { 296 compatible = "renesas,scif-r9a07g044"; 297 reg = <0 0x1004c000 0 0x400>; 298 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 304 interrupt-names = "eri", "rxi", "txi", 305 "bri", "dri", "tei"; 306 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; 307 clock-names = "fck"; 308 power-domains = <&cpg>; 309 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; 310 status = "disabled"; 311 }; 312 313 scif3: serial@1004c400 { 314 compatible = "renesas,scif-r9a07g044"; 315 reg = <0 0x1004c400 0 0x400>; 316 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 322 interrupt-names = "eri", "rxi", "txi", 323 "bri", "dri", "tei"; 324 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; 325 clock-names = "fck"; 326 power-domains = <&cpg>; 327 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; 328 status = "disabled"; 329 }; 330 331 scif4: serial@1004c800 { 332 compatible = "renesas,scif-r9a07g044"; 333 reg = <0 0x1004c800 0 0x400>; 334 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "eri", "rxi", "txi", 341 "bri", "dri", "tei"; 342 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; 343 clock-names = "fck"; 344 power-domains = <&cpg>; 345 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; 346 status = "disabled"; 347 }; 348 349 sci0: serial@1004d000 { 350 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 351 reg = <0 0x1004d000 0 0x400>; 352 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 356 interrupt-names = "eri", "rxi", "txi", "tei"; 357 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; 358 clock-names = "fck"; 359 power-domains = <&cpg>; 360 resets = <&cpg R9A07G044_SCI0_RST>; 361 status = "disabled"; 362 }; 363 364 sci1: serial@1004d400 { 365 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 366 reg = <0 0x1004d400 0 0x400>; 367 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "eri", "rxi", "txi", "tei"; 372 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; 373 clock-names = "fck"; 374 power-domains = <&cpg>; 375 resets = <&cpg R9A07G044_SCI1_RST>; 376 status = "disabled"; 377 }; 378 379 canfd: can@10050000 { 380 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; 381 reg = <0 0x10050000 0 0x8000>; 382 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-names = "g_err", "g_recc", 391 "ch0_err", "ch0_rec", "ch0_trx", 392 "ch1_err", "ch1_rec", "ch1_trx"; 393 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, 394 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, 395 <&can_clk>; 396 clock-names = "fck", "canfd", "can_clk"; 397 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; 398 assigned-clock-rates = <50000000>; 399 resets = <&cpg R9A07G044_CANFD_RSTP_N>, 400 <&cpg R9A07G044_CANFD_RSTC_N>; 401 reset-names = "rstp_n", "rstc_n"; 402 power-domains = <&cpg>; 403 status = "disabled"; 404 405 channel0 { 406 status = "disabled"; 407 }; 408 channel1 { 409 status = "disabled"; 410 }; 411 }; 412 413 i2c0: i2c@10058000 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 417 reg = <0 0x10058000 0 0x400>; 418 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "tei", "ri", "ti", "spi", "sti", 427 "naki", "ali", "tmoi"; 428 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; 429 clock-frequency = <100000>; 430 resets = <&cpg R9A07G044_I2C0_MRST>; 431 power-domains = <&cpg>; 432 status = "disabled"; 433 }; 434 435 i2c1: i2c@10058400 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 439 reg = <0 0x10058400 0 0x400>; 440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 448 interrupt-names = "tei", "ri", "ti", "spi", "sti", 449 "naki", "ali", "tmoi"; 450 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; 451 clock-frequency = <100000>; 452 resets = <&cpg R9A07G044_I2C1_MRST>; 453 power-domains = <&cpg>; 454 status = "disabled"; 455 }; 456 457 i2c2: i2c@10058800 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 461 reg = <0 0x10058800 0 0x400>; 462 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 464 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 465 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "tei", "ri", "ti", "spi", "sti", 471 "naki", "ali", "tmoi"; 472 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; 473 clock-frequency = <100000>; 474 resets = <&cpg R9A07G044_I2C2_MRST>; 475 power-domains = <&cpg>; 476 status = "disabled"; 477 }; 478 479 i2c3: i2c@10058c00 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 483 reg = <0 0x10058c00 0 0x400>; 484 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "tei", "ri", "ti", "spi", "sti", 493 "naki", "ali", "tmoi"; 494 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; 495 clock-frequency = <100000>; 496 resets = <&cpg R9A07G044_I2C3_MRST>; 497 power-domains = <&cpg>; 498 status = "disabled"; 499 }; 500 501 adc: adc@10059000 { 502 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; 503 reg = <0 0x10059000 0 0x400>; 504 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 505 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, 506 <&cpg CPG_MOD R9A07G044_ADC_PCLK>; 507 clock-names = "adclk", "pclk"; 508 resets = <&cpg R9A07G044_ADC_PRESETN>, 509 <&cpg R9A07G044_ADC_ADRST_N>; 510 reset-names = "presetn", "adrst-n"; 511 power-domains = <&cpg>; 512 status = "disabled"; 513 514 #address-cells = <1>; 515 #size-cells = <0>; 516 517 channel@0 { 518 reg = <0>; 519 }; 520 channel@1 { 521 reg = <1>; 522 }; 523 channel@2 { 524 reg = <2>; 525 }; 526 channel@3 { 527 reg = <3>; 528 }; 529 channel@4 { 530 reg = <4>; 531 }; 532 channel@5 { 533 reg = <5>; 534 }; 535 channel@6 { 536 reg = <6>; 537 }; 538 channel@7 { 539 reg = <7>; 540 }; 541 }; 542 543 tsu: thermal@10059400 { 544 compatible = "renesas,r9a07g044-tsu", 545 "renesas,rzg2l-tsu"; 546 reg = <0 0x10059400 0 0x400>; 547 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; 548 resets = <&cpg R9A07G044_TSU_PRESETN>; 549 power-domains = <&cpg>; 550 #thermal-sensor-cells = <1>; 551 }; 552 553 sbc: spi@10060000 { 554 compatible = "renesas,r9a07g044-rpc-if", 555 "renesas,rzg2l-rpc-if"; 556 reg = <0 0x10060000 0 0x10000>, 557 <0 0x20000000 0 0x10000000>, 558 <0 0x10070000 0 0x10000>; 559 reg-names = "regs", "dirmap", "wbuf"; 560 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, 562 <&cpg CPG_MOD R9A07G044_SPI_CLK>; 563 resets = <&cpg R9A07G044_SPI_RST>; 564 power-domains = <&cpg>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 status = "disabled"; 568 }; 569 570 cpg: clock-controller@11010000 { 571 compatible = "renesas,r9a07g044-cpg"; 572 reg = <0 0x11010000 0 0x10000>; 573 clocks = <&extal_clk>; 574 clock-names = "extal"; 575 #clock-cells = <2>; 576 #reset-cells = <1>; 577 #power-domain-cells = <0>; 578 }; 579 580 sysc: system-controller@11020000 { 581 compatible = "renesas,r9a07g044-sysc"; 582 reg = <0 0x11020000 0 0x10000>; 583 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "lpm_int", "ca55stbydone_int", 588 "cm33stbyr_int", "ca55_deny"; 589 status = "disabled"; 590 }; 591 592 pinctrl: pin-controller@11030000 { 593 compatible = "renesas,r9a07g044-pinctrl"; 594 reg = <0 0x11030000 0 0x10000>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 gpio-ranges = <&pinctrl 0 0 392>; 598 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 599 power-domains = <&cpg>; 600 resets = <&cpg R9A07G044_GPIO_RSTN>, 601 <&cpg R9A07G044_GPIO_PORT_RESETN>, 602 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 603 }; 604 605 dmac: dma-controller@11820000 { 606 compatible = "renesas,r9a07g044-dmac", 607 "renesas,rz-dmac"; 608 reg = <0 0x11820000 0 0x10000>, 609 <0 0x11830000 0 0x10000>; 610 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 611 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 612 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 613 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 614 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 615 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 616 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 617 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 618 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 619 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 621 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 622 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 623 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 624 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 625 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 626 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 627 interrupt-names = "error", 628 "ch0", "ch1", "ch2", "ch3", 629 "ch4", "ch5", "ch6", "ch7", 630 "ch8", "ch9", "ch10", "ch11", 631 "ch12", "ch13", "ch14", "ch15"; 632 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 633 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 634 power-domains = <&cpg>; 635 resets = <&cpg R9A07G044_DMAC_ARESETN>, 636 <&cpg R9A07G044_DMAC_RST_ASYNC>; 637 #dma-cells = <1>; 638 dma-channels = <16>; 639 }; 640 641 gic: interrupt-controller@11900000 { 642 compatible = "arm,gic-v3"; 643 #interrupt-cells = <3>; 644 #address-cells = <0>; 645 interrupt-controller; 646 reg = <0x0 0x11900000 0 0x40000>, 647 <0x0 0x11940000 0 0x60000>; 648 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 649 }; 650 651 sdhi0: mmc@11c00000 { 652 compatible = "renesas,sdhi-r9a07g044", 653 "renesas,rcar-gen3-sdhi"; 654 reg = <0x0 0x11c00000 0 0x10000>; 655 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, 658 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, 659 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, 660 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; 661 clock-names = "core", "clkh", "cd", "aclk"; 662 resets = <&cpg R9A07G044_SDHI0_IXRST>; 663 power-domains = <&cpg>; 664 status = "disabled"; 665 }; 666 667 sdhi1: mmc@11c10000 { 668 compatible = "renesas,sdhi-r9a07g044", 669 "renesas,rcar-gen3-sdhi"; 670 reg = <0x0 0x11c10000 0 0x10000>; 671 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, 674 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, 675 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, 676 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; 677 clock-names = "core", "clkh", "cd", "aclk"; 678 resets = <&cpg R9A07G044_SDHI1_IXRST>; 679 power-domains = <&cpg>; 680 status = "disabled"; 681 }; 682 683 eth0: ethernet@11c20000 { 684 compatible = "renesas,r9a07g044-gbeth", 685 "renesas,rzg2l-gbeth"; 686 reg = <0 0x11c20000 0 0x10000>; 687 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "mux", "fil", "arp_ns"; 691 phy-mode = "rgmii"; 692 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, 693 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, 694 <&cpg CPG_CORE R9A07G044_CLK_HP>; 695 clock-names = "axi", "chi", "refclk"; 696 resets = <&cpg R9A07G044_ETH0_RST_HW_N>; 697 power-domains = <&cpg>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 eth1: ethernet@11c30000 { 704 compatible = "renesas,r9a07g044-gbeth", 705 "renesas,rzg2l-gbeth"; 706 reg = <0 0x11c30000 0 0x10000>; 707 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 710 interrupt-names = "mux", "fil", "arp_ns"; 711 phy-mode = "rgmii"; 712 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, 713 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, 714 <&cpg CPG_CORE R9A07G044_CLK_HP>; 715 clock-names = "axi", "chi", "refclk"; 716 resets = <&cpg R9A07G044_ETH1_RST_HW_N>; 717 power-domains = <&cpg>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 status = "disabled"; 721 }; 722 723 phyrst: usbphy-ctrl@11c40000 { 724 compatible = "renesas,r9a07g044-usbphy-ctrl", 725 "renesas,rzg2l-usbphy-ctrl"; 726 reg = <0 0x11c40000 0 0x10000>; 727 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 728 resets = <&cpg R9A07G044_USB_PRESETN>; 729 power-domains = <&cpg>; 730 #reset-cells = <1>; 731 status = "disabled"; 732 }; 733 734 ohci0: usb@11c50000 { 735 compatible = "generic-ohci"; 736 reg = <0 0x11c50000 0 0x100>; 737 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 739 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 740 resets = <&phyrst 0>, 741 <&cpg R9A07G044_USB_U2H0_HRESETN>; 742 phys = <&usb2_phy0 1>; 743 phy-names = "usb"; 744 power-domains = <&cpg>; 745 status = "disabled"; 746 }; 747 748 ohci1: usb@11c70000 { 749 compatible = "generic-ohci"; 750 reg = <0 0x11c70000 0 0x100>; 751 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 753 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 754 resets = <&phyrst 1>, 755 <&cpg R9A07G044_USB_U2H1_HRESETN>; 756 phys = <&usb2_phy1 1>; 757 phy-names = "usb"; 758 power-domains = <&cpg>; 759 status = "disabled"; 760 }; 761 762 ehci0: usb@11c50100 { 763 compatible = "generic-ehci"; 764 reg = <0 0x11c50100 0 0x100>; 765 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 767 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 768 resets = <&phyrst 0>, 769 <&cpg R9A07G044_USB_U2H0_HRESETN>; 770 phys = <&usb2_phy0 2>; 771 phy-names = "usb"; 772 companion = <&ohci0>; 773 power-domains = <&cpg>; 774 status = "disabled"; 775 }; 776 777 ehci1: usb@11c70100 { 778 compatible = "generic-ehci"; 779 reg = <0 0x11c70100 0 0x100>; 780 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 782 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 783 resets = <&phyrst 1>, 784 <&cpg R9A07G044_USB_U2H1_HRESETN>; 785 phys = <&usb2_phy1 2>; 786 phy-names = "usb"; 787 companion = <&ohci1>; 788 power-domains = <&cpg>; 789 status = "disabled"; 790 }; 791 792 usb2_phy0: usb-phy@11c50200 { 793 compatible = "renesas,usb2-phy-r9a07g044", 794 "renesas,rzg2l-usb2-phy"; 795 reg = <0 0x11c50200 0 0x700>; 796 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 798 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 799 resets = <&phyrst 0>; 800 #phy-cells = <1>; 801 power-domains = <&cpg>; 802 status = "disabled"; 803 }; 804 805 usb2_phy1: usb-phy@11c70200 { 806 compatible = "renesas,usb2-phy-r9a07g044", 807 "renesas,rzg2l-usb2-phy"; 808 reg = <0 0x11c70200 0 0x700>; 809 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 811 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 812 resets = <&phyrst 1>; 813 #phy-cells = <1>; 814 power-domains = <&cpg>; 815 status = "disabled"; 816 }; 817 818 hsusb: usb@11c60000 { 819 compatible = "renesas,usbhs-r9a07g044", 820 "renesas,rza2-usbhs"; 821 reg = <0 0x11c60000 0 0x10000>; 822 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 823 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 827 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>; 828 resets = <&phyrst 0>, 829 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>; 830 renesas,buswait = <7>; 831 phys = <&usb2_phy0 3>; 832 phy-names = "usb"; 833 power-domains = <&cpg>; 834 status = "disabled"; 835 }; 836 837 wdt0: watchdog@12800800 { 838 compatible = "renesas,r9a07g044-wdt", 839 "renesas,rzg2l-wdt"; 840 reg = <0 0x12800800 0 0x400>; 841 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, 842 <&cpg CPG_MOD R9A07G044_WDT0_CLK>; 843 clock-names = "pclk", "oscclk"; 844 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "wdt", "perrout"; 847 resets = <&cpg R9A07G044_WDT0_PRESETN>; 848 power-domains = <&cpg>; 849 status = "disabled"; 850 }; 851 852 wdt1: watchdog@12800c00 { 853 compatible = "renesas,r9a07g044-wdt", 854 "renesas,rzg2l-wdt"; 855 reg = <0 0x12800C00 0 0x400>; 856 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, 857 <&cpg CPG_MOD R9A07G044_WDT1_CLK>; 858 clock-names = "pclk", "oscclk"; 859 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "wdt", "perrout"; 862 resets = <&cpg R9A07G044_WDT1_PRESETN>; 863 power-domains = <&cpg>; 864 status = "disabled"; 865 }; 866 867 wdt2: watchdog@12800400 { 868 compatible = "renesas,r9a07g044-wdt", 869 "renesas,rzg2l-wdt"; 870 reg = <0 0x12800400 0 0x400>; 871 clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>, 872 <&cpg CPG_MOD R9A07G044_WDT2_CLK>; 873 clock-names = "pclk", "oscclk"; 874 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "wdt", "perrout"; 877 resets = <&cpg R9A07G044_WDT2_PRESETN>; 878 power-domains = <&cpg>; 879 status = "disabled"; 880 }; 881 882 ostm0: timer@12801000 { 883 compatible = "renesas,r9a07g044-ostm", 884 "renesas,ostm"; 885 reg = <0x0 0x12801000 0x0 0x400>; 886 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 887 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; 888 resets = <&cpg R9A07G044_OSTM0_PRESETZ>; 889 power-domains = <&cpg>; 890 status = "disabled"; 891 }; 892 893 ostm1: timer@12801400 { 894 compatible = "renesas,r9a07g044-ostm", 895 "renesas,ostm"; 896 reg = <0x0 0x12801400 0x0 0x400>; 897 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 898 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; 899 resets = <&cpg R9A07G044_OSTM1_PRESETZ>; 900 power-domains = <&cpg>; 901 status = "disabled"; 902 }; 903 904 ostm2: timer@12801800 { 905 compatible = "renesas,r9a07g044-ostm", 906 "renesas,ostm"; 907 reg = <0x0 0x12801800 0x0 0x400>; 908 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 909 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; 910 resets = <&cpg R9A07G044_OSTM2_PRESETZ>; 911 power-domains = <&cpg>; 912 status = "disabled"; 913 }; 914 }; 915 916 thermal-zones { 917 cpu-thermal { 918 polling-delay-passive = <250>; 919 polling-delay = <1000>; 920 thermal-sensors = <&tsu 0>; 921 sustainable-power = <717>; 922 923 cooling-maps { 924 map0 { 925 trip = <&target>; 926 cooling-device = <&cpu0 0 2>; 927 contribution = <1024>; 928 }; 929 }; 930 931 trips { 932 sensor_crit: sensor-crit { 933 temperature = <125000>; 934 hysteresis = <1000>; 935 type = "critical"; 936 }; 937 938 target: trip-point { 939 temperature = <100000>; 940 hysteresis = <1000>; 941 type = "passive"; 942 }; 943 }; 944 }; 945 }; 946 947 timer { 948 compatible = "arm,armv8-timer"; 949 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 950 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 951 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 952 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 953 }; 954}; 955