1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g044-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g044"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 cache-level = <3>; 113 }; 114 }; 115 116 gpu_opp_table: opp-table-1 { 117 compatible = "operating-points-v2"; 118 119 opp-500000000 { 120 opp-hz = /bits/ 64 <500000000>; 121 opp-microvolt = <1100000>; 122 }; 123 124 opp-400000000 { 125 opp-hz = /bits/ 64 <400000000>; 126 opp-microvolt = <1100000>; 127 }; 128 129 opp-250000000 { 130 opp-hz = /bits/ 64 <250000000>; 131 opp-microvolt = <1100000>; 132 }; 133 134 opp-200000000 { 135 opp-hz = /bits/ 64 <200000000>; 136 opp-microvolt = <1100000>; 137 }; 138 139 opp-125000000 { 140 opp-hz = /bits/ 64 <125000000>; 141 opp-microvolt = <1100000>; 142 }; 143 144 opp-100000000 { 145 opp-hz = /bits/ 64 <100000000>; 146 opp-microvolt = <1100000>; 147 }; 148 149 opp-62500000 { 150 opp-hz = /bits/ 64 <62500000>; 151 opp-microvolt = <1100000>; 152 }; 153 154 opp-50000000 { 155 opp-hz = /bits/ 64 <50000000>; 156 opp-microvolt = <1100000>; 157 }; 158 }; 159 160 pmu { 161 compatible = "arm,cortex-a55-pmu"; 162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 163 }; 164 165 psci { 166 compatible = "arm,psci-1.0", "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 soc: soc { 171 compatible = "simple-bus"; 172 interrupt-parent = <&gic>; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 177 ssi0: ssi@10049c00 { 178 compatible = "renesas,r9a07g044-ssi", 179 "renesas,rz-ssi"; 180 reg = <0 0x10049c00 0 0x400>; 181 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 183 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 185 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 186 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, 187 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, 188 <&audio_clk1>, <&audio_clk2>; 189 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 190 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; 191 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 192 dma-names = "tx", "rx"; 193 power-domains = <&cpg>; 194 #sound-dai-cells = <0>; 195 status = "disabled"; 196 }; 197 198 ssi1: ssi@1004a000 { 199 compatible = "renesas,r9a07g044-ssi", 200 "renesas,rz-ssi"; 201 reg = <0 0x1004a000 0 0x400>; 202 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 204 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 205 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 206 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 207 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, 208 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, 209 <&audio_clk1>, <&audio_clk2>; 210 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 211 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; 212 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 213 dma-names = "tx", "rx"; 214 power-domains = <&cpg>; 215 #sound-dai-cells = <0>; 216 status = "disabled"; 217 }; 218 219 ssi2: ssi@1004a400 { 220 compatible = "renesas,r9a07g044-ssi", 221 "renesas,rz-ssi"; 222 reg = <0 0x1004a400 0 0x400>; 223 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 225 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 226 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 227 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 228 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, 229 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, 230 <&audio_clk1>, <&audio_clk2>; 231 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 232 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; 233 dmas = <&dmac 0x265f>; 234 dma-names = "rt"; 235 power-domains = <&cpg>; 236 #sound-dai-cells = <0>; 237 status = "disabled"; 238 }; 239 240 ssi3: ssi@1004a800 { 241 compatible = "renesas,r9a07g044-ssi", 242 "renesas,rz-ssi"; 243 reg = <0 0x1004a800 0 0x400>; 244 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 246 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 247 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 248 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 249 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, 250 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, 251 <&audio_clk1>, <&audio_clk2>; 252 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 253 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; 254 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 255 dma-names = "tx", "rx"; 256 power-domains = <&cpg>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 }; 260 261 spi0: spi@1004ac00 { 262 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 263 reg = <0 0x1004ac00 0 0x400>; 264 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 267 interrupt-names = "error", "rx", "tx"; 268 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; 269 resets = <&cpg R9A07G044_RSPI0_RST>; 270 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 271 dma-names = "tx", "rx"; 272 power-domains = <&cpg>; 273 num-cs = <1>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 status = "disabled"; 277 }; 278 279 spi1: spi@1004b000 { 280 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 281 reg = <0 0x1004b000 0 0x400>; 282 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "error", "rx", "tx"; 286 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; 287 resets = <&cpg R9A07G044_RSPI1_RST>; 288 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 289 dma-names = "tx", "rx"; 290 power-domains = <&cpg>; 291 num-cs = <1>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 spi2: spi@1004b400 { 298 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 299 reg = <0 0x1004b400 0 0x400>; 300 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 303 interrupt-names = "error", "rx", "tx"; 304 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; 305 resets = <&cpg R9A07G044_RSPI2_RST>; 306 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 307 dma-names = "tx", "rx"; 308 power-domains = <&cpg>; 309 num-cs = <1>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 scif0: serial@1004b800 { 316 compatible = "renesas,scif-r9a07g044"; 317 reg = <0 0x1004b800 0 0x400>; 318 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "eri", "rxi", "txi", 325 "bri", "dri", "tei"; 326 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; 327 clock-names = "fck"; 328 power-domains = <&cpg>; 329 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; 330 status = "disabled"; 331 }; 332 333 scif1: serial@1004bc00 { 334 compatible = "renesas,scif-r9a07g044"; 335 reg = <0 0x1004bc00 0 0x400>; 336 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "eri", "rxi", "txi", 343 "bri", "dri", "tei"; 344 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; 345 clock-names = "fck"; 346 power-domains = <&cpg>; 347 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; 348 status = "disabled"; 349 }; 350 351 scif2: serial@1004c000 { 352 compatible = "renesas,scif-r9a07g044"; 353 reg = <0 0x1004c000 0 0x400>; 354 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "eri", "rxi", "txi", 361 "bri", "dri", "tei"; 362 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; 363 clock-names = "fck"; 364 power-domains = <&cpg>; 365 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; 366 status = "disabled"; 367 }; 368 369 scif3: serial@1004c400 { 370 compatible = "renesas,scif-r9a07g044"; 371 reg = <0 0x1004c400 0 0x400>; 372 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "eri", "rxi", "txi", 379 "bri", "dri", "tei"; 380 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; 381 clock-names = "fck"; 382 power-domains = <&cpg>; 383 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; 384 status = "disabled"; 385 }; 386 387 scif4: serial@1004c800 { 388 compatible = "renesas,scif-r9a07g044"; 389 reg = <0 0x1004c800 0 0x400>; 390 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 396 interrupt-names = "eri", "rxi", "txi", 397 "bri", "dri", "tei"; 398 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; 399 clock-names = "fck"; 400 power-domains = <&cpg>; 401 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; 402 status = "disabled"; 403 }; 404 405 sci0: serial@1004d000 { 406 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 407 reg = <0 0x1004d000 0 0x400>; 408 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 412 interrupt-names = "eri", "rxi", "txi", "tei"; 413 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; 414 clock-names = "fck"; 415 power-domains = <&cpg>; 416 resets = <&cpg R9A07G044_SCI0_RST>; 417 status = "disabled"; 418 }; 419 420 sci1: serial@1004d400 { 421 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 422 reg = <0 0x1004d400 0 0x400>; 423 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 427 interrupt-names = "eri", "rxi", "txi", "tei"; 428 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; 429 clock-names = "fck"; 430 power-domains = <&cpg>; 431 resets = <&cpg R9A07G044_SCI1_RST>; 432 status = "disabled"; 433 }; 434 435 canfd: can@10050000 { 436 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; 437 reg = <0 0x10050000 0 0x8000>; 438 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "g_err", "g_recc", 447 "ch0_err", "ch0_rec", "ch0_trx", 448 "ch1_err", "ch1_rec", "ch1_trx"; 449 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, 450 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, 451 <&can_clk>; 452 clock-names = "fck", "canfd", "can_clk"; 453 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; 454 assigned-clock-rates = <50000000>; 455 resets = <&cpg R9A07G044_CANFD_RSTP_N>, 456 <&cpg R9A07G044_CANFD_RSTC_N>; 457 reset-names = "rstp_n", "rstc_n"; 458 power-domains = <&cpg>; 459 status = "disabled"; 460 461 channel0 { 462 status = "disabled"; 463 }; 464 channel1 { 465 status = "disabled"; 466 }; 467 }; 468 469 i2c0: i2c@10058000 { 470 #address-cells = <1>; 471 #size-cells = <0>; 472 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 473 reg = <0 0x10058000 0 0x400>; 474 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "tei", "ri", "ti", "spi", "sti", 483 "naki", "ali", "tmoi"; 484 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; 485 clock-frequency = <100000>; 486 resets = <&cpg R9A07G044_I2C0_MRST>; 487 power-domains = <&cpg>; 488 status = "disabled"; 489 }; 490 491 i2c1: i2c@10058400 { 492 #address-cells = <1>; 493 #size-cells = <0>; 494 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 495 reg = <0 0x10058400 0 0x400>; 496 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 498 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 499 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "tei", "ri", "ti", "spi", "sti", 505 "naki", "ali", "tmoi"; 506 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; 507 clock-frequency = <100000>; 508 resets = <&cpg R9A07G044_I2C1_MRST>; 509 power-domains = <&cpg>; 510 status = "disabled"; 511 }; 512 513 i2c2: i2c@10058800 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 517 reg = <0 0x10058800 0 0x400>; 518 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 521 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 526 interrupt-names = "tei", "ri", "ti", "spi", "sti", 527 "naki", "ali", "tmoi"; 528 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; 529 clock-frequency = <100000>; 530 resets = <&cpg R9A07G044_I2C2_MRST>; 531 power-domains = <&cpg>; 532 status = "disabled"; 533 }; 534 535 i2c3: i2c@10058c00 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 539 reg = <0 0x10058c00 0 0x400>; 540 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "tei", "ri", "ti", "spi", "sti", 549 "naki", "ali", "tmoi"; 550 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; 551 clock-frequency = <100000>; 552 resets = <&cpg R9A07G044_I2C3_MRST>; 553 power-domains = <&cpg>; 554 status = "disabled"; 555 }; 556 557 adc: adc@10059000 { 558 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; 559 reg = <0 0x10059000 0 0x400>; 560 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 561 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, 562 <&cpg CPG_MOD R9A07G044_ADC_PCLK>; 563 clock-names = "adclk", "pclk"; 564 resets = <&cpg R9A07G044_ADC_PRESETN>, 565 <&cpg R9A07G044_ADC_ADRST_N>; 566 reset-names = "presetn", "adrst-n"; 567 power-domains = <&cpg>; 568 status = "disabled"; 569 570 #address-cells = <1>; 571 #size-cells = <0>; 572 573 channel@0 { 574 reg = <0>; 575 }; 576 channel@1 { 577 reg = <1>; 578 }; 579 channel@2 { 580 reg = <2>; 581 }; 582 channel@3 { 583 reg = <3>; 584 }; 585 channel@4 { 586 reg = <4>; 587 }; 588 channel@5 { 589 reg = <5>; 590 }; 591 channel@6 { 592 reg = <6>; 593 }; 594 channel@7 { 595 reg = <7>; 596 }; 597 }; 598 599 tsu: thermal@10059400 { 600 compatible = "renesas,r9a07g044-tsu", 601 "renesas,rzg2l-tsu"; 602 reg = <0 0x10059400 0 0x400>; 603 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; 604 resets = <&cpg R9A07G044_TSU_PRESETN>; 605 power-domains = <&cpg>; 606 #thermal-sensor-cells = <1>; 607 }; 608 609 sbc: spi@10060000 { 610 compatible = "renesas,r9a07g044-rpc-if", 611 "renesas,rzg2l-rpc-if"; 612 reg = <0 0x10060000 0 0x10000>, 613 <0 0x20000000 0 0x10000000>, 614 <0 0x10070000 0 0x10000>; 615 reg-names = "regs", "dirmap", "wbuf"; 616 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, 618 <&cpg CPG_MOD R9A07G044_SPI_CLK>; 619 resets = <&cpg R9A07G044_SPI_RST>; 620 power-domains = <&cpg>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 cpg: clock-controller@11010000 { 627 compatible = "renesas,r9a07g044-cpg"; 628 reg = <0 0x11010000 0 0x10000>; 629 clocks = <&extal_clk>; 630 clock-names = "extal"; 631 #clock-cells = <2>; 632 #reset-cells = <1>; 633 #power-domain-cells = <0>; 634 }; 635 636 sysc: system-controller@11020000 { 637 compatible = "renesas,r9a07g044-sysc"; 638 reg = <0 0x11020000 0 0x10000>; 639 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 643 interrupt-names = "lpm_int", "ca55stbydone_int", 644 "cm33stbyr_int", "ca55_deny"; 645 status = "disabled"; 646 }; 647 648 pinctrl: pinctrl@11030000 { 649 compatible = "renesas,r9a07g044-pinctrl"; 650 reg = <0 0x11030000 0 0x10000>; 651 gpio-controller; 652 #gpio-cells = <2>; 653 #interrupt-cells = <2>; 654 interrupt-parent = <&irqc>; 655 interrupt-controller; 656 gpio-ranges = <&pinctrl 0 0 392>; 657 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 658 power-domains = <&cpg>; 659 resets = <&cpg R9A07G044_GPIO_RSTN>, 660 <&cpg R9A07G044_GPIO_PORT_RESETN>, 661 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 662 }; 663 664 irqc: interrupt-controller@110a0000 { 665 compatible = "renesas,r9a07g044-irqc", 666 "renesas,rzg2l-irqc"; 667 #interrupt-cells = <2>; 668 #address-cells = <0>; 669 interrupt-controller; 670 reg = <0 0x110a0000 0 0x10000>; 671 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, 713 <&cpg CPG_MOD R9A07G044_IA55_PCLK>; 714 clock-names = "clk", "pclk"; 715 power-domains = <&cpg>; 716 resets = <&cpg R9A07G044_IA55_RESETN>; 717 }; 718 719 dmac: dma-controller@11820000 { 720 compatible = "renesas,r9a07g044-dmac", 721 "renesas,rz-dmac"; 722 reg = <0 0x11820000 0 0x10000>, 723 <0 0x11830000 0 0x10000>; 724 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 725 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 726 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 727 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 728 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 729 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 730 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 731 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 732 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 733 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 734 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 735 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 736 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 737 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 738 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 739 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 740 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 741 interrupt-names = "error", 742 "ch0", "ch1", "ch2", "ch3", 743 "ch4", "ch5", "ch6", "ch7", 744 "ch8", "ch9", "ch10", "ch11", 745 "ch12", "ch13", "ch14", "ch15"; 746 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 747 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 748 power-domains = <&cpg>; 749 resets = <&cpg R9A07G044_DMAC_ARESETN>, 750 <&cpg R9A07G044_DMAC_RST_ASYNC>; 751 #dma-cells = <1>; 752 dma-channels = <16>; 753 }; 754 755 gpu: gpu@11840000 { 756 compatible = "renesas,r9a07g044-mali", 757 "arm,mali-bifrost"; 758 reg = <0x0 0x11840000 0x0 0x10000>; 759 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 763 interrupt-names = "job", "mmu", "gpu", "event"; 764 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, 765 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, 766 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; 767 clock-names = "gpu", "bus", "bus_ace"; 768 power-domains = <&cpg>; 769 resets = <&cpg R9A07G044_GPU_RESETN>, 770 <&cpg R9A07G044_GPU_AXI_RESETN>, 771 <&cpg R9A07G044_GPU_ACE_RESETN>; 772 reset-names = "rst", "axi_rst", "ace_rst"; 773 operating-points-v2 = <&gpu_opp_table>; 774 }; 775 776 gic: interrupt-controller@11900000 { 777 compatible = "arm,gic-v3"; 778 #interrupt-cells = <3>; 779 #address-cells = <0>; 780 interrupt-controller; 781 reg = <0x0 0x11900000 0 0x40000>, 782 <0x0 0x11940000 0 0x60000>; 783 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 784 }; 785 786 sdhi0: mmc@11c00000 { 787 compatible = "renesas,sdhi-r9a07g044", 788 "renesas,rcar-gen3-sdhi"; 789 reg = <0x0 0x11c00000 0 0x10000>; 790 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, 793 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, 794 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, 795 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; 796 clock-names = "core", "clkh", "cd", "aclk"; 797 resets = <&cpg R9A07G044_SDHI0_IXRST>; 798 power-domains = <&cpg>; 799 status = "disabled"; 800 }; 801 802 sdhi1: mmc@11c10000 { 803 compatible = "renesas,sdhi-r9a07g044", 804 "renesas,rcar-gen3-sdhi"; 805 reg = <0x0 0x11c10000 0 0x10000>; 806 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, 809 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, 810 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, 811 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; 812 clock-names = "core", "clkh", "cd", "aclk"; 813 resets = <&cpg R9A07G044_SDHI1_IXRST>; 814 power-domains = <&cpg>; 815 status = "disabled"; 816 }; 817 818 eth0: ethernet@11c20000 { 819 compatible = "renesas,r9a07g044-gbeth", 820 "renesas,rzg2l-gbeth"; 821 reg = <0 0x11c20000 0 0x10000>; 822 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "mux", "fil", "arp_ns"; 826 phy-mode = "rgmii"; 827 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, 828 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, 829 <&cpg CPG_CORE R9A07G044_CLK_HP>; 830 clock-names = "axi", "chi", "refclk"; 831 resets = <&cpg R9A07G044_ETH0_RST_HW_N>; 832 power-domains = <&cpg>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 eth1: ethernet@11c30000 { 839 compatible = "renesas,r9a07g044-gbeth", 840 "renesas,rzg2l-gbeth"; 841 reg = <0 0x11c30000 0 0x10000>; 842 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 845 interrupt-names = "mux", "fil", "arp_ns"; 846 phy-mode = "rgmii"; 847 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, 848 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, 849 <&cpg CPG_CORE R9A07G044_CLK_HP>; 850 clock-names = "axi", "chi", "refclk"; 851 resets = <&cpg R9A07G044_ETH1_RST_HW_N>; 852 power-domains = <&cpg>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 phyrst: usbphy-ctrl@11c40000 { 859 compatible = "renesas,r9a07g044-usbphy-ctrl", 860 "renesas,rzg2l-usbphy-ctrl"; 861 reg = <0 0x11c40000 0 0x10000>; 862 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 863 resets = <&cpg R9A07G044_USB_PRESETN>; 864 power-domains = <&cpg>; 865 #reset-cells = <1>; 866 status = "disabled"; 867 }; 868 869 ohci0: usb@11c50000 { 870 compatible = "generic-ohci"; 871 reg = <0 0x11c50000 0 0x100>; 872 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 874 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 875 resets = <&phyrst 0>, 876 <&cpg R9A07G044_USB_U2H0_HRESETN>; 877 phys = <&usb2_phy0 1>; 878 phy-names = "usb"; 879 power-domains = <&cpg>; 880 status = "disabled"; 881 }; 882 883 ohci1: usb@11c70000 { 884 compatible = "generic-ohci"; 885 reg = <0 0x11c70000 0 0x100>; 886 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 888 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 889 resets = <&phyrst 1>, 890 <&cpg R9A07G044_USB_U2H1_HRESETN>; 891 phys = <&usb2_phy1 1>; 892 phy-names = "usb"; 893 power-domains = <&cpg>; 894 status = "disabled"; 895 }; 896 897 ehci0: usb@11c50100 { 898 compatible = "generic-ehci"; 899 reg = <0 0x11c50100 0 0x100>; 900 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 902 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 903 resets = <&phyrst 0>, 904 <&cpg R9A07G044_USB_U2H0_HRESETN>; 905 phys = <&usb2_phy0 2>; 906 phy-names = "usb"; 907 companion = <&ohci0>; 908 power-domains = <&cpg>; 909 status = "disabled"; 910 }; 911 912 ehci1: usb@11c70100 { 913 compatible = "generic-ehci"; 914 reg = <0 0x11c70100 0 0x100>; 915 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 917 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 918 resets = <&phyrst 1>, 919 <&cpg R9A07G044_USB_U2H1_HRESETN>; 920 phys = <&usb2_phy1 2>; 921 phy-names = "usb"; 922 companion = <&ohci1>; 923 power-domains = <&cpg>; 924 status = "disabled"; 925 }; 926 927 usb2_phy0: usb-phy@11c50200 { 928 compatible = "renesas,usb2-phy-r9a07g044", 929 "renesas,rzg2l-usb2-phy"; 930 reg = <0 0x11c50200 0 0x700>; 931 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 933 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 934 resets = <&phyrst 0>; 935 #phy-cells = <1>; 936 power-domains = <&cpg>; 937 status = "disabled"; 938 }; 939 940 usb2_phy1: usb-phy@11c70200 { 941 compatible = "renesas,usb2-phy-r9a07g044", 942 "renesas,rzg2l-usb2-phy"; 943 reg = <0 0x11c70200 0 0x700>; 944 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 946 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 947 resets = <&phyrst 1>; 948 #phy-cells = <1>; 949 power-domains = <&cpg>; 950 status = "disabled"; 951 }; 952 953 hsusb: usb@11c60000 { 954 compatible = "renesas,usbhs-r9a07g044", 955 "renesas,rza2-usbhs"; 956 reg = <0 0x11c60000 0 0x10000>; 957 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 958 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 962 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>; 963 resets = <&phyrst 0>, 964 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>; 965 renesas,buswait = <7>; 966 phys = <&usb2_phy0 3>; 967 phy-names = "usb"; 968 power-domains = <&cpg>; 969 status = "disabled"; 970 }; 971 972 wdt0: watchdog@12800800 { 973 compatible = "renesas,r9a07g044-wdt", 974 "renesas,rzg2l-wdt"; 975 reg = <0 0x12800800 0 0x400>; 976 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, 977 <&cpg CPG_MOD R9A07G044_WDT0_CLK>; 978 clock-names = "pclk", "oscclk"; 979 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 981 interrupt-names = "wdt", "perrout"; 982 resets = <&cpg R9A07G044_WDT0_PRESETN>; 983 power-domains = <&cpg>; 984 status = "disabled"; 985 }; 986 987 wdt1: watchdog@12800c00 { 988 compatible = "renesas,r9a07g044-wdt", 989 "renesas,rzg2l-wdt"; 990 reg = <0 0x12800C00 0 0x400>; 991 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, 992 <&cpg CPG_MOD R9A07G044_WDT1_CLK>; 993 clock-names = "pclk", "oscclk"; 994 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 996 interrupt-names = "wdt", "perrout"; 997 resets = <&cpg R9A07G044_WDT1_PRESETN>; 998 power-domains = <&cpg>; 999 status = "disabled"; 1000 }; 1001 1002 ostm0: timer@12801000 { 1003 compatible = "renesas,r9a07g044-ostm", 1004 "renesas,ostm"; 1005 reg = <0x0 0x12801000 0x0 0x400>; 1006 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 1007 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; 1008 resets = <&cpg R9A07G044_OSTM0_PRESETZ>; 1009 power-domains = <&cpg>; 1010 status = "disabled"; 1011 }; 1012 1013 ostm1: timer@12801400 { 1014 compatible = "renesas,r9a07g044-ostm", 1015 "renesas,ostm"; 1016 reg = <0x0 0x12801400 0x0 0x400>; 1017 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 1018 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; 1019 resets = <&cpg R9A07G044_OSTM1_PRESETZ>; 1020 power-domains = <&cpg>; 1021 status = "disabled"; 1022 }; 1023 1024 ostm2: timer@12801800 { 1025 compatible = "renesas,r9a07g044-ostm", 1026 "renesas,ostm"; 1027 reg = <0x0 0x12801800 0x0 0x400>; 1028 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 1029 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; 1030 resets = <&cpg R9A07G044_OSTM2_PRESETZ>; 1031 power-domains = <&cpg>; 1032 status = "disabled"; 1033 }; 1034 }; 1035 1036 thermal-zones { 1037 cpu-thermal { 1038 polling-delay-passive = <250>; 1039 polling-delay = <1000>; 1040 thermal-sensors = <&tsu 0>; 1041 sustainable-power = <717>; 1042 1043 cooling-maps { 1044 map0 { 1045 trip = <&target>; 1046 cooling-device = <&cpu0 0 2>; 1047 contribution = <1024>; 1048 }; 1049 }; 1050 1051 trips { 1052 sensor_crit: sensor-crit { 1053 temperature = <125000>; 1054 hysteresis = <1000>; 1055 type = "critical"; 1056 }; 1057 1058 target: trip-point { 1059 temperature = <100000>; 1060 hysteresis = <1000>; 1061 type = "passive"; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 timer { 1068 compatible = "arm,armv8-timer"; 1069 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1070 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1071 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1072 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1073 }; 1074}; 1075