Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33 |
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#
2f00bb4a |
| 07-Apr-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: marvell: align SPI NOR node name with dtschema
The node names should be generic and SPI NOR dtschema expects "flash".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
arm64: dts: marvell: align SPI NOR node name with dtschema
The node names should be generic and SPI NOR dtschema expects "flash".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407143234.295426-2-krzysztof.kozlowski@linaro.org
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Revision tags: v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
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#
45b25653 |
| 08-Jul-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada
Change all 10G port modes in Armada family device trees from 10gbase-kr to 10gbase-r
Signed-off-by: Konstantin Porotchkin <kostap@marvell.c
arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada
Change all 10G port modes in Armada family device trees from 10gbase-kr to 10gbase-r
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22 |
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#
99fa8ac5 |
| 07-Mar-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arm64: dts: marvell: enable CP110 UTMI PHY usage
Enable support for CP110 UTMI PHY in Armada SoC family platform device trees.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-b
arm64: dts: marvell: enable CP110 UTMI PHY usage
Enable support for CP110 UTMI PHY in Armada SoC family platform device trees.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6 |
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#
96018a6f |
| 31-Jul-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent) generic PHY framework instead of the (legacy) usb-phy prepe
arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent) generic PHY framework instead of the (legacy) usb-phy preperty. Both enable the supply when the PHY is enabled.
The COMPHY nodes only provide SERDES lanes configuration. The power supply that is represented by the phy-supply property is just a regulator wired to the USB connector, hence the creation of connector nodes as child of the COMPHY nodes and the supply attached to it.
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
ce55522c |
| 31-Jul-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k based boards.
The MacchiatoBin is a bit particular as the Armada8k-PCI IP sup
arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k based boards.
The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports x4 link widths and in this case the PHY for each lane must be referenced.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
01d0deba |
| 31-Jul-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k based boards. Only update nodes actually enabling USB3 in the default (mainlin
arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k based boards. Only update nodes actually enabling USB3 in the default (mainline) configuration. A few USB nodes are enabled but there is only USB2 working on them.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
d04abe99 |
| 31-Jul-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.co
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4 |
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#
d8cc5cf0 |
| 21-May-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
arm64: dts: marvell: Disable AP I2C on Armada-8040-DB
While AP I2C bus was available to users in early revisions of the SoC, this is not the case anymore since eMMC was connected to the AP. Most use
arm64: dts: marvell: Disable AP I2C on Armada-8040-DB
While AP I2C bus was available to users in early revisions of the SoC, this is not the case anymore since eMMC was connected to the AP. Most users do not have access to this I2C bus so do not enable it in the board device tree.
As there are three I2C buses enabled on this board, add an alias to be sure the two other buses keep their initial numbering.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [<miquel.raynal@bootlin.com>: Reword commit message, add alias] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20 |
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#
8b0a14d9 |
| 05-Feb-2019 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes
By using the new binding for the partitions for the flashes we don't need anymore to use #size-cells and #address-cel
arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes
By using the new binding for the partitions for the flashes we don't need anymore to use #size-cells and #address-cells at the flash node level.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17 |
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#
639585ac |
| 17-May-2018 |
Antoine Tenart <antoine.tenart@bootlin.com> |
arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-link
This patch adds a fixed-link node to both 10G interfaces of the 8040-db board. This is required as the mvpp2 driver now uses p
arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-link
This patch adds a fixed-link node to both 10G interfaces of the 8040-db board. This is required as the mvpp2 driver now uses phylink. The best solution would have been to describe the SFP cages but they are not wired correctly, and thus unusable, so we chose to use fixed-link instead.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.16 |
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#
41d63e45 |
| 19-Feb-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: use reworked NAND controller driver on Armada 8K
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to disting
arm64: dts: marvell: use reworked NAND controller driver on Armada 8K
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the driver activates the arbiter by default for all boards (either needed or harmless).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
4e6a62b6 |
| 14-Feb-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
arm64: dts: marvell: armada-8040-db: use SPDX-License-Identifier
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT.
As already pointed on the DT ML, th
arm64: dts: marvell: armada-8040-db: use SPDX-License-Identifier
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.15 |
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#
474c5885 |
| 03-Jan-2018 |
Yan Markman <ymarkman@marvell.com> |
arm64: dts: marvell: add Ethernet aliases
This patch adds Ethernet aliases in the Marvell Armada 7040 DB, 8040 DB and 8040 mcbin device trees so that the bootloader setup the MAC addresses correctly
arm64: dts: marvell: add Ethernet aliases
This patch adds Ethernet aliases in the Marvell Armada 7040 DB, 8040 DB and 8040 mcbin device trees so that the bootloader setup the MAC addresses correctly.
Signed-off-by: Yan Markman <ymarkman@marvell.com> [Antoine: commit message, small fixes] Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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#
91f1be92 |
| 02-Jan-2018 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
arm64: dts: marvell: replace cpm by cp0, cps by cp1
In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cp
arm64: dts: marvell: replace cpm by cp0, cps by cp1
In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1.
This commit is the result of:
sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/*
So it is a purely mechaninal change.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Revision tags: v4.13.16, v4.14 |
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#
7b31e3ad |
| 30-Oct-2017 |
Miquel Raynal <miquel.raynal@free-electrons.com> |
arm64: dts: marvell: add NAND support on the 8040-DB board
Add NAND support on the Armada-8040-DB by adding the same tree as for the Armada-7040-DB by using the same compatible string "marvell,armad
arm64: dts: marvell: add NAND support on the 8040-DB board
Add NAND support on the Armada-8040-DB by adding the same tree as for the Armada-7040-DB by using the same compatible string "marvell,armada-8k-nand".
Do not enable the NAND node as enabling it (and changing manually the proper DPR-76 switch) would disable MDIO from CP1 (and thus disable CPS Ethernet PHY).
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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#
d8bcaabe |
| 13-Oct-2017 |
Rob Herring <robh@kernel.org> |
arm64: dts: fix unit-address leading 0s
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot
arm64: dts: fix unit-address leading 0s
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*'
Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v4.13.5 |
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#
30571678 |
| 28-Sep-2017 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DB
The Armada 8040 DB has numerous PCIe ports, so let's enable a few more of those PCIe ports that are enabled in the default bootloa
arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DB
The Armada 8040 DB has numerous PCIe ports, so let's enable a few more of those PCIe ports that are enabled in the default bootloader configuration.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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#
441fadad |
| 22-Sep-2017 |
Christine Gharzuzi <chrisg@marvell.com> |
arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1
Add the DT node enabling Armada-8040-DB CPS SPI controller driver.
Add the SPI NAND flash device connected on the bus. Fill the MTD partitions la
arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1
Add the DT node enabling Armada-8040-DB CPS SPI controller driver.
Add the SPI NAND flash device connected on the bus. Fill the MTD partitions layout.
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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#
0539cbb5 |
| 21-Sep-2017 |
Antoine Tenart <antoine.tenart@free-electrons.com> |
arm64: dts: marvell: 8040-db: enable the SFP ports
This patch enables the SFP ports on the Armada 8040 DB as these ports are now supported by the PPv2 driver (since the PHY is now optional).
Signed
arm64: dts: marvell: 8040-db: enable the SFP ports
This patch enables the SFP ports on the Armada 8040 DB as these ports are now supported by the PPv2 driver (since the PHY is now optional).
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Revision tags: v4.13 |
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9e83bbdb |
| 30-Aug-2017 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
arm64: dts: marvell: add UART muxing on Armada 7K/8K
This commit adds the relevant details in the Armada 7K/8K Device Tree to properly mux the UART used for the serial console. Since there is basica
arm64: dts: marvell: add UART muxing on Armada 7K/8K
This commit adds the relevant details in the Armada 7K/8K Device Tree to properly mux the UART used for the serial console. Since there is basically only one possible muxing for the UART0 on the AP, the muxing configuration is described in armada-ap806.dtsi, and selected from the individual boards (other boards could be using a different UART).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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0ea62502 |
| 09-Aug-2017 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
ARM64: dts: marvell: enable USB host on Armada-8040-DB
Enable USB host on Armada-8040-DB by adding USB PHY nodes for the following ports: - host 0 and 1 of CPM - host 0 of CPS
These PHY are ena
ARM64: dts: marvell: enable USB host on Armada-8040-DB
Enable USB host on Armada-8040-DB by adding USB PHY nodes for the following ports: - host 0 and 1 of CPM - host 0 of CPS
These PHY are enabled by lanes coming from regulators based on two I2C expanders.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Revision tags: v4.12 |
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b97afaf6 |
| 15-Jun-2017 |
Antoine Tenart <antoine.tenart@free-electrons.com> |
arm64: dts: marvell: remove cpm crypto nodes from dts files
The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it.
arm64: dts: marvell: remove cpm crypto nodes from dts files
The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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3c6912cd |
| 08-Jun-2017 |
Antoine Tenart <antoine.tenart@free-electrons.com> |
arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DB
Explicitly enable the MDIO nodes in the Marvell Armada 7k DB and Marvell Armada 8k DB. This is needed as the MDIO nodes will be dis
arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DB
Explicitly enable the MDIO nodes in the Marvell Armada 7k DB and Marvell Armada 8k DB. This is needed as the MDIO nodes will be disabled in the CP 110 slave and master dtsi by a following up patch.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Revision tags: v4.10.17 |
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4f08187d |
| 15-May-2017 |
Marcin Wojtas <mw@semihalf.com> |
arm64: dts: marvell: add second 1G port on the Armada 8040 DB
Armada 8040 DB is equipped with 4 (2x 10G SFI + 2x 1G RGMII) ethernet ports of which only one was hitherto enabled. Because currently mv
arm64: dts: marvell: add second 1G port on the Armada 8040 DB
Armada 8040 DB is equipped with 4 (2x 10G SFI + 2x 1G RGMII) ethernet ports of which only one was hitherto enabled. Because currently mvpp2 driver is capable of supporting only 1G RGMII/SGMII, enable second port from CP slave HW block.
Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Revision tags: v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7 |
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7ba2ef7c |
| 29-Mar-2017 |
Antoine Tenart <antoine.tenart@free-electrons.com> |
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
Enable the cryptographic engine available in the CP110 master on the Armada 8040 DB. Do not enable the one in the CP110 salve for
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
Enable the cryptographic engine available in the CP110 master on the Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we do not support multiple cryptographic engines yet.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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