1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada 8040 Development board platform 45 */ 46 47#include <dt-bindings/gpio/gpio.h> 48#include "armada-8040.dtsi" 49 50/ { 51 model = "Marvell Armada 8040 DB board"; 52 compatible = "marvell,armada8040-db", "marvell,armada8040", 53 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 54 55 chosen { 56 stdout-path = "serial0:115200n8"; 57 }; 58 59 memory@0 { 60 device_type = "memory"; 61 reg = <0x0 0x0 0x0 0x80000000>; 62 }; 63 64 aliases { 65 ethernet0 = &cp0_eth0; 66 ethernet1 = &cp0_eth2; 67 ethernet2 = &cp1_eth0; 68 ethernet3 = &cp1_eth1; 69 }; 70 71 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 72 compatible = "regulator-fixed"; 73 regulator-name = "cp0-usb3h0-vbus"; 74 regulator-min-microvolt = <5000000>; 75 regulator-max-microvolt = <5000000>; 76 enable-active-high; 77 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 78 }; 79 80 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 81 compatible = "regulator-fixed"; 82 regulator-name = "cp0-usb3h1-vbus"; 83 regulator-min-microvolt = <5000000>; 84 regulator-max-microvolt = <5000000>; 85 enable-active-high; 86 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 87 }; 88 89 cp0_usb3_0_phy: cp0-usb3-0-phy { 90 compatible = "usb-nop-xceiv"; 91 vcc-supply = <&cp0_reg_usb3_0_vbus>; 92 }; 93 94 cp0_usb3_1_phy: cp0-usb3-1-phy { 95 compatible = "usb-nop-xceiv"; 96 vcc-supply = <&cp0_reg_usb3_1_vbus>; 97 }; 98 99 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { 100 compatible = "regulator-fixed"; 101 regulator-name = "cp1-usb3h0-vbus"; 102 regulator-min-microvolt = <5000000>; 103 regulator-max-microvolt = <5000000>; 104 enable-active-high; 105 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; 106 }; 107 108 cp1_usb3_0_phy: cp1-usb3-0-phy { 109 compatible = "usb-nop-xceiv"; 110 vcc-supply = <&cp1_reg_usb3_0_vbus>; 111 }; 112}; 113 114&i2c0 { 115 status = "okay"; 116 clock-frequency = <100000>; 117}; 118 119&spi0 { 120 status = "okay"; 121 122 spi-flash@0 { 123 #address-cells = <1>; 124 #size-cells = <1>; 125 compatible = "jedec,spi-nor"; 126 reg = <0>; 127 spi-max-frequency = <10000000>; 128 129 partitions { 130 compatible = "fixed-partitions"; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 134 partition@0 { 135 label = "U-Boot"; 136 reg = <0 0x200000>; 137 }; 138 partition@400000 { 139 label = "Filesystem"; 140 reg = <0x200000 0xce0000>; 141 }; 142 }; 143 }; 144}; 145 146/* Accessible over the mini-USB CON9 connector on the main board */ 147&uart0 { 148 status = "okay"; 149 pinctrl-0 = <&uart0_pins>; 150 pinctrl-names = "default"; 151}; 152 153/* CON6 on CP0 expansion */ 154&cp0_pcie0 { 155 status = "okay"; 156}; 157 158/* CON5 on CP0 expansion */ 159&cp0_pcie2 { 160 status = "okay"; 161}; 162 163&cp0_i2c0 { 164 status = "okay"; 165 clock-frequency = <100000>; 166 167 /* U31 */ 168 expander0: pca9555@21 { 169 compatible = "nxp,pca9555"; 170 pinctrl-names = "default"; 171 gpio-controller; 172 #gpio-cells = <2>; 173 reg = <0x21>; 174 }; 175 176 /* U25 */ 177 expander1: pca9555@25 { 178 compatible = "nxp,pca9555"; 179 pinctrl-names = "default"; 180 gpio-controller; 181 #gpio-cells = <2>; 182 reg = <0x25>; 183 }; 184 185}; 186 187/* CON4 on CP0 expansion */ 188&cp0_sata0 { 189 status = "okay"; 190}; 191 192/* CON9 on CP0 expansion */ 193&cp0_usb3_0 { 194 usb-phy = <&cp0_usb3_0_phy>; 195 status = "okay"; 196}; 197 198/* CON10 on CP0 expansion */ 199&cp0_usb3_1 { 200 usb-phy = <&cp0_usb3_1_phy>; 201 status = "okay"; 202}; 203 204&cp0_mdio { 205 status = "okay"; 206 207 phy1: ethernet-phy@1 { 208 reg = <1>; 209 }; 210}; 211 212&cp0_ethernet { 213 status = "okay"; 214}; 215 216&cp0_eth0 { 217 status = "okay"; 218 phy-mode = "10gbase-kr"; 219}; 220 221&cp0_eth2 { 222 status = "okay"; 223 phy = <&phy1>; 224 phy-mode = "rgmii-id"; 225}; 226 227/* CON6 on CP1 expansion */ 228&cp1_pcie0 { 229 status = "okay"; 230}; 231 232/* CON7 on CP1 expansion */ 233&cp1_pcie1 { 234 status = "okay"; 235}; 236 237/* CON5 on CP1 expansion */ 238&cp1_pcie2 { 239 status = "okay"; 240}; 241 242&cp1_i2c0 { 243 status = "okay"; 244 clock-frequency = <100000>; 245}; 246 247&cp1_spi1 { 248 status = "okay"; 249 250 spi-flash@0 { 251 #address-cells = <0x1>; 252 #size-cells = <0x1>; 253 compatible = "jedec,spi-nor"; 254 reg = <0x0>; 255 spi-max-frequency = <20000000>; 256 257 partitions { 258 compatible = "fixed-partitions"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 partition@0 { 263 label = "Boot"; 264 reg = <0x0 0x200000>; 265 }; 266 partition@200000 { 267 label = "Filesystem"; 268 reg = <0x200000 0xd00000>; 269 }; 270 partition@f00000 { 271 label = "Boot_2nd"; 272 reg = <0xf00000 0x100000>; 273 }; 274 }; 275 }; 276}; 277 278/* 279 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables 280 * MDIO signal of CP1. 281 */ 282&cp1_nand { 283 num-cs = <1>; 284 pinctrl-0 = <&nand_pins>, <&nand_rb>; 285 pinctrl-names = "default"; 286 nand-ecc-strength = <4>; 287 nand-ecc-step-size = <512>; 288 marvell,nand-enable-arbiter; 289 marvell,system-controller = <&cp1_syscon0>; 290 nand-on-flash-bbt; 291 292 partition@0 { 293 label = "U-Boot"; 294 reg = <0 0x200000>; 295 }; 296 partition@200000 { 297 label = "Linux"; 298 reg = <0x200000 0xe00000>; 299 }; 300 partition@1000000 { 301 label = "Filesystem"; 302 reg = <0x1000000 0x3f000000>; 303 }; 304}; 305 306/* CON4 on CP1 expansion */ 307&cp1_sata0 { 308 status = "okay"; 309}; 310 311/* CON9 on CP1 expansion */ 312&cp1_usb3_0 { 313 usb-phy = <&cp1_usb3_0_phy>; 314 status = "okay"; 315}; 316 317/* CON10 on CP1 expansion */ 318&cp1_usb3_1 { 319 status = "okay"; 320}; 321 322&cp1_mdio { 323 status = "okay"; 324 325 phy0: ethernet-phy@0 { 326 reg = <0>; 327 }; 328}; 329 330&cp1_ethernet { 331 status = "okay"; 332}; 333 334&cp1_eth0 { 335 status = "okay"; 336 phy-mode = "10gbase-kr"; 337}; 338 339&cp1_eth1 { 340 status = "okay"; 341 phy = <&phy0>; 342 phy-mode = "rgmii-id"; 343}; 344 345&ap_sdhci0 { 346 status = "okay"; 347 bus-width = <4>; 348 non-removable; 349}; 350 351&cp0_sdhci0 { 352 status = "okay"; 353 bus-width = <8>; 354 non-removable; 355}; 356