1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada 8040 Development board platform 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include "armada-8040.dtsi" 10 11/ { 12 model = "Marvell Armada 8040 DB board"; 13 compatible = "marvell,armada8040-db", "marvell,armada8040", 14 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15 16 chosen { 17 stdout-path = "serial0:115200n8"; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x0 0x0 0x0 0x80000000>; 23 }; 24 25 aliases { 26 ethernet0 = &cp0_eth0; 27 ethernet1 = &cp0_eth2; 28 ethernet2 = &cp1_eth0; 29 ethernet3 = &cp1_eth1; 30 i2c1 = &cp0_i2c0; 31 i2c2 = &cp1_i2c0; 32 }; 33 34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 35 compatible = "regulator-fixed"; 36 regulator-name = "cp0-usb3h0-vbus"; 37 regulator-min-microvolt = <5000000>; 38 regulator-max-microvolt = <5000000>; 39 enable-active-high; 40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 41 }; 42 43 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 44 compatible = "regulator-fixed"; 45 regulator-name = "cp0-usb3h1-vbus"; 46 regulator-min-microvolt = <5000000>; 47 regulator-max-microvolt = <5000000>; 48 enable-active-high; 49 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 50 }; 51 52 cp0_usb3_0_phy: cp0-usb3-0-phy { 53 compatible = "usb-nop-xceiv"; 54 vcc-supply = <&cp0_reg_usb3_0_vbus>; 55 }; 56 57 cp0_usb3_1_phy: cp0-usb3-1-phy { 58 compatible = "usb-nop-xceiv"; 59 vcc-supply = <&cp0_reg_usb3_1_vbus>; 60 }; 61 62 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { 63 compatible = "regulator-fixed"; 64 regulator-name = "cp1-usb3h0-vbus"; 65 regulator-min-microvolt = <5000000>; 66 regulator-max-microvolt = <5000000>; 67 enable-active-high; 68 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; 69 }; 70 71 cp1_usb3_0_phy: cp1-usb3-0-phy { 72 compatible = "usb-nop-xceiv"; 73 vcc-supply = <&cp1_reg_usb3_0_vbus>; 74 }; 75}; 76 77&spi0 { 78 status = "okay"; 79 80 spi-flash@0 { 81 compatible = "jedec,spi-nor"; 82 reg = <0>; 83 spi-max-frequency = <10000000>; 84 85 partitions { 86 compatible = "fixed-partitions"; 87 #address-cells = <1>; 88 #size-cells = <1>; 89 90 partition@0 { 91 label = "U-Boot"; 92 reg = <0 0x200000>; 93 }; 94 partition@400000 { 95 label = "Filesystem"; 96 reg = <0x200000 0xce0000>; 97 }; 98 }; 99 }; 100}; 101 102/* Accessible over the mini-USB CON9 connector on the main board */ 103&uart0 { 104 status = "okay"; 105 pinctrl-0 = <&uart0_pins>; 106 pinctrl-names = "default"; 107}; 108 109/* CON6 on CP0 expansion */ 110&cp0_pcie0 { 111 phys = <&cp0_comphy0 0>; 112 phy-names = "cp0-pcie0-x1-phy"; 113 status = "okay"; 114}; 115 116/* CON5 on CP0 expansion */ 117&cp0_pcie2 { 118 phys = <&cp0_comphy5 2>; 119 phy-names = "cp0-pcie2-x1-phy"; 120 status = "okay"; 121}; 122 123&cp0_i2c0 { 124 status = "okay"; 125 clock-frequency = <100000>; 126 127 /* U31 */ 128 expander0: pca9555@21 { 129 compatible = "nxp,pca9555"; 130 pinctrl-names = "default"; 131 gpio-controller; 132 #gpio-cells = <2>; 133 reg = <0x21>; 134 }; 135 136 /* U25 */ 137 expander1: pca9555@25 { 138 compatible = "nxp,pca9555"; 139 pinctrl-names = "default"; 140 gpio-controller; 141 #gpio-cells = <2>; 142 reg = <0x25>; 143 }; 144 145}; 146 147/* CON4 on CP0 expansion */ 148&cp0_sata0 { 149 status = "okay"; 150 151 sata-port@0 { 152 phys = <&cp0_comphy1 0>; 153 phy-names = "cp0-sata0-0-phy"; 154 }; 155 sata-port@1 { 156 phys = <&cp0_comphy3 1>; 157 phy-names = "cp0-sata0-1-phy"; 158 }; 159}; 160 161/* CON9 on CP0 expansion */ 162&cp0_usb3_0 { 163 usb-phy = <&cp0_usb3_0_phy>; 164 status = "okay"; 165}; 166 167/* CON10 on CP0 expansion */ 168&cp0_usb3_1 { 169 usb-phy = <&cp0_usb3_1_phy>; 170 phys = <&cp0_comphy4 1>; 171 phy-names = "cp0-usb3h1-comphy"; 172 status = "okay"; 173}; 174 175&cp0_mdio { 176 status = "okay"; 177 178 phy1: ethernet-phy@1 { 179 reg = <1>; 180 }; 181}; 182 183&cp0_ethernet { 184 status = "okay"; 185}; 186 187&cp0_eth0 { 188 status = "okay"; 189 phy-mode = "10gbase-kr"; 190 191 fixed-link { 192 speed = <10000>; 193 full-duplex; 194 }; 195}; 196 197&cp0_eth2 { 198 status = "okay"; 199 phy = <&phy1>; 200 phy-mode = "rgmii-id"; 201}; 202 203/* CON6 on CP1 expansion */ 204&cp1_pcie0 { 205 phys = <&cp1_comphy0 0>; 206 phy-names = "cp1-pcie0-x1-phy"; 207 status = "okay"; 208}; 209 210/* CON7 on CP1 expansion */ 211&cp1_pcie1 { 212 phys = <&cp1_comphy4 1>; 213 phy-names = "cp1-pcie1-x1-phy"; 214 status = "okay"; 215}; 216 217/* CON5 on CP1 expansion */ 218&cp1_pcie2 { 219 phys = <&cp1_comphy5 2>; 220 phy-names = "cp1-pcie2-x1-phy"; 221 status = "okay"; 222}; 223 224&cp1_i2c0 { 225 status = "okay"; 226 clock-frequency = <100000>; 227}; 228 229&cp1_spi1 { 230 status = "okay"; 231 232 spi-flash@0 { 233 compatible = "jedec,spi-nor"; 234 reg = <0x0>; 235 spi-max-frequency = <20000000>; 236 237 partitions { 238 compatible = "fixed-partitions"; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 242 partition@0 { 243 label = "Boot"; 244 reg = <0x0 0x200000>; 245 }; 246 partition@200000 { 247 label = "Filesystem"; 248 reg = <0x200000 0xd00000>; 249 }; 250 partition@f00000 { 251 label = "Boot_2nd"; 252 reg = <0xf00000 0x100000>; 253 }; 254 }; 255 }; 256}; 257 258/* 259 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables 260 * MDIO signal of CP1. 261 */ 262&cp1_nand_controller { 263 pinctrl-0 = <&nand_pins>, <&nand_rb>; 264 pinctrl-names = "default"; 265 266 nand@0 { 267 reg = <0>; 268 nand-rb = <0>; 269 nand-on-flash-bbt; 270 nand-ecc-strength = <4>; 271 nand-ecc-step-size = <512>; 272 273 partitions { 274 compatible = "fixed-partitions"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 278 partition@0 { 279 label = "U-Boot"; 280 reg = <0 0x200000>; 281 }; 282 partition@200000 { 283 label = "Linux"; 284 reg = <0x200000 0xe00000>; 285 }; 286 partition@1000000 { 287 label = "Filesystem"; 288 reg = <0x1000000 0x3f000000>; 289 }; 290 }; 291 }; 292}; 293 294/* CON4 on CP1 expansion */ 295&cp1_sata0 { 296 status = "okay"; 297 298 sata-port@0 { 299 phys = <&cp1_comphy1 0>; 300 phy-names = "cp1-sata0-0-phy"; 301 }; 302 sata-port@1 { 303 phys = <&cp1_comphy3 1>; 304 phy-names = "cp1-sata0-1-phy"; 305 }; 306}; 307 308/* CON9 on CP1 expansion */ 309&cp1_usb3_0 { 310 usb-phy = <&cp1_usb3_0_phy>; 311 status = "okay"; 312}; 313 314/* CON10 on CP1 expansion */ 315&cp1_usb3_1 { 316 status = "okay"; 317}; 318 319&cp1_mdio { 320 status = "okay"; 321 322 phy0: ethernet-phy@0 { 323 reg = <0>; 324 }; 325}; 326 327&cp1_ethernet { 328 status = "okay"; 329}; 330 331&cp1_eth0 { 332 status = "okay"; 333 phy-mode = "10gbase-kr"; 334 335 fixed-link { 336 speed = <10000>; 337 full-duplex; 338 }; 339}; 340 341&cp1_eth1 { 342 status = "okay"; 343 phy = <&phy0>; 344 phy-mode = "rgmii-id"; 345}; 346 347&ap_sdhci0 { 348 status = "okay"; 349 bus-width = <4>; 350 non-removable; 351}; 352 353&cp0_sdhci0 { 354 status = "okay"; 355 bus-width = <8>; 356 non-removable; 357}; 358