1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada 8040 Development board platform
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include "armada-8040.dtsi"
10
11/ {
12	model = "Marvell Armada 8040 DB board";
13	compatible = "marvell,armada8040-db", "marvell,armada8040",
14		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0x0 0x0 0x0 0x80000000>;
23	};
24
25	aliases {
26		ethernet0 = &cp0_eth0;
27		ethernet1 = &cp0_eth2;
28		ethernet2 = &cp1_eth0;
29		ethernet3 = &cp1_eth1;
30		i2c1 = &cp0_i2c0;
31		i2c2 = &cp1_i2c0;
32	};
33
34	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35		compatible = "regulator-fixed";
36		regulator-name = "cp0-usb3h0-vbus";
37		regulator-min-microvolt = <5000000>;
38		regulator-max-microvolt = <5000000>;
39		enable-active-high;
40		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41	};
42
43	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
44		compatible = "regulator-fixed";
45		regulator-name = "cp0-usb3h1-vbus";
46		regulator-min-microvolt = <5000000>;
47		regulator-max-microvolt = <5000000>;
48		enable-active-high;
49		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50	};
51
52	cp0_usb3_0_phy: cp0-usb3-0-phy {
53		compatible = "usb-nop-xceiv";
54		vcc-supply = <&cp0_reg_usb3_0_vbus>;
55	};
56
57	cp0_usb3_1_phy: cp0-usb3-1-phy {
58		compatible = "usb-nop-xceiv";
59		vcc-supply = <&cp0_reg_usb3_1_vbus>;
60	};
61
62	cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63		compatible = "regulator-fixed";
64		regulator-name = "cp1-usb3h0-vbus";
65		regulator-min-microvolt = <5000000>;
66		regulator-max-microvolt = <5000000>;
67		enable-active-high;
68		gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
69	};
70
71	cp1_usb3_0_phy: cp1-usb3-0-phy {
72		compatible = "usb-nop-xceiv";
73		vcc-supply = <&cp1_reg_usb3_0_vbus>;
74	};
75};
76
77&spi0 {
78	status = "okay";
79
80	spi-flash@0 {
81		compatible = "jedec,spi-nor";
82		reg = <0>;
83		spi-max-frequency = <10000000>;
84
85		partitions {
86			compatible = "fixed-partitions";
87			#address-cells = <1>;
88			#size-cells = <1>;
89
90			partition@0 {
91				label = "U-Boot";
92				reg = <0 0x200000>;
93			};
94			partition@400000 {
95				label = "Filesystem";
96				reg = <0x200000 0xce0000>;
97			};
98		};
99	};
100};
101
102/* Accessible over the mini-USB CON9 connector on the main board */
103&uart0 {
104	status = "okay";
105	pinctrl-0 = <&uart0_pins>;
106	pinctrl-names = "default";
107};
108
109/* CON6 on CP0 expansion */
110&cp0_pcie0 {
111	status = "okay";
112};
113
114/* CON5 on CP0 expansion */
115&cp0_pcie2 {
116	status = "okay";
117};
118
119&cp0_i2c0 {
120	status = "okay";
121	clock-frequency = <100000>;
122
123	/* U31 */
124	expander0: pca9555@21 {
125		compatible = "nxp,pca9555";
126		pinctrl-names = "default";
127		gpio-controller;
128		#gpio-cells = <2>;
129		reg = <0x21>;
130	};
131
132	/* U25 */
133	expander1: pca9555@25 {
134		compatible = "nxp,pca9555";
135		pinctrl-names = "default";
136		gpio-controller;
137		#gpio-cells = <2>;
138		reg = <0x25>;
139	};
140
141};
142
143/* CON4 on CP0 expansion */
144&cp0_sata0 {
145	status = "okay";
146
147	sata-port@0 {
148		phys = <&cp0_comphy1 0>;
149		phy-names = "cp0-sata0-0-phy";
150	};
151	sata-port@1 {
152		phys = <&cp0_comphy3 1>;
153		phy-names = "cp0-sata0-1-phy";
154	};
155};
156
157/* CON9 on CP0 expansion */
158&cp0_usb3_0 {
159	usb-phy = <&cp0_usb3_0_phy>;
160	status = "okay";
161};
162
163/* CON10 on CP0 expansion */
164&cp0_usb3_1 {
165	usb-phy = <&cp0_usb3_1_phy>;
166	status = "okay";
167};
168
169&cp0_mdio {
170	status = "okay";
171
172	phy1: ethernet-phy@1 {
173		reg = <1>;
174	};
175};
176
177&cp0_ethernet {
178	status = "okay";
179};
180
181&cp0_eth0 {
182	status = "okay";
183	phy-mode = "10gbase-kr";
184
185	fixed-link {
186		speed = <10000>;
187		full-duplex;
188	};
189};
190
191&cp0_eth2 {
192	status = "okay";
193	phy = <&phy1>;
194	phy-mode = "rgmii-id";
195};
196
197/* CON6 on CP1 expansion */
198&cp1_pcie0 {
199	status = "okay";
200};
201
202/* CON7 on CP1 expansion */
203&cp1_pcie1 {
204	status = "okay";
205};
206
207/* CON5 on CP1 expansion */
208&cp1_pcie2 {
209	status = "okay";
210};
211
212&cp1_i2c0 {
213	status = "okay";
214	clock-frequency = <100000>;
215};
216
217&cp1_spi1 {
218	status = "okay";
219
220	spi-flash@0 {
221		compatible = "jedec,spi-nor";
222		reg = <0x0>;
223		spi-max-frequency = <20000000>;
224
225		partitions {
226			compatible = "fixed-partitions";
227			#address-cells = <1>;
228			#size-cells = <1>;
229
230			partition@0 {
231				label = "Boot";
232				reg = <0x0 0x200000>;
233			};
234			partition@200000 {
235				label = "Filesystem";
236				reg = <0x200000 0xd00000>;
237			};
238			partition@f00000 {
239				label = "Boot_2nd";
240				reg = <0xf00000 0x100000>;
241			};
242		};
243	};
244};
245
246/*
247 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
248 * MDIO signal of CP1.
249 */
250&cp1_nand_controller {
251	pinctrl-0 = <&nand_pins>, <&nand_rb>;
252	pinctrl-names = "default";
253
254	nand@0 {
255		reg = <0>;
256		nand-rb = <0>;
257		nand-on-flash-bbt;
258		nand-ecc-strength = <4>;
259		nand-ecc-step-size = <512>;
260
261		partitions {
262			compatible = "fixed-partitions";
263			#address-cells = <1>;
264			#size-cells = <1>;
265
266			partition@0 {
267				label = "U-Boot";
268				reg = <0 0x200000>;
269			};
270			partition@200000 {
271				label = "Linux";
272				reg = <0x200000 0xe00000>;
273			};
274			partition@1000000 {
275				label = "Filesystem";
276				reg = <0x1000000 0x3f000000>;
277			};
278		};
279	};
280};
281
282/* CON4 on CP1 expansion */
283&cp1_sata0 {
284	status = "okay";
285
286	sata-port@0 {
287		phys = <&cp1_comphy1 0>;
288		phy-names = "cp1-sata0-0-phy";
289	};
290	sata-port@1 {
291		phys = <&cp1_comphy3 1>;
292		phy-names = "cp1-sata0-1-phy";
293	};
294};
295
296/* CON9 on CP1 expansion */
297&cp1_usb3_0 {
298	usb-phy = <&cp1_usb3_0_phy>;
299	status = "okay";
300};
301
302/* CON10 on CP1 expansion */
303&cp1_usb3_1 {
304	status = "okay";
305};
306
307&cp1_mdio {
308	status = "okay";
309
310	phy0: ethernet-phy@0 {
311		reg = <0>;
312	};
313};
314
315&cp1_ethernet {
316	status = "okay";
317};
318
319&cp1_eth0 {
320	status = "okay";
321	phy-mode = "10gbase-kr";
322
323	fixed-link {
324		speed = <10000>;
325		full-duplex;
326	};
327};
328
329&cp1_eth1 {
330	status = "okay";
331	phy = <&phy0>;
332	phy-mode = "rgmii-id";
333};
334
335&ap_sdhci0 {
336	status = "okay";
337	bus-width = <4>;
338	non-removable;
339};
340
341&cp0_sdhci0 {
342	status = "okay";
343	bus-width = <8>;
344	non-removable;
345};
346