|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3 |
|
| #
c2258a94 |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: amlogic: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
meson-a1-ad401.dtb: l2-cache0: 'cache-
arm64: dts: amlogic: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
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|
Revision tags: v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11 |
|
| #
18b542e5 |
| 02-Dec-2022 |
Tomeu Vizoso <tomeu.vizoso@collabora.com> |
arm64: dts: Add DT node for the VIPNano-QI on the A311D
This "NPU" is very similar to the Vivante GPUs and Etnaviv works well
with it with just a few small changes.
v2: Add reference to RESET_NNA (
arm64: dts: Add DT node for the VIPNano-QI on the A311D
This "NPU" is very similar to the Vivante GPUs and Etnaviv works well
with it with just a few small changes.
v2: Add reference to RESET_NNA (Neil)
v3: Fix indentation (Neil)
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20221202115223.39051-5-tomeu.vizoso@collabora.com
[narmstrong: squash patch 8, disable NPU by default and do not enable NPU on vim3 yet]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
|
|
Revision tags: v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
|
| #
90cf8e21 |
| 08-Nov-2022 |
Jiucheng Xu <jiucheng.xu@amlogic.com> |
arm64: dts: meson: Add DDR PMU node
Add DDR PMU device node for G12 series SoC
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: htt
arm64: dts: meson: Add DDR PMU node
Add DDR PMU device node for G12 series SoC
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20221109015818.194927-4-jiucheng.xu@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
|
| #
49f65e2e |
| 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: Update cache properties for amlogic
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Sha
arm64: dts: Update cache properties for amlogic
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-4-pierre.gondois@arm.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
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|
Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
|
| #
03544505 |
| 22-Sep-2020 |
Robin Murphy <robin.murphy@arm.com> |
arm64: dts: meson: Describe G12b GPU as coherent
According to a downstream commit I found in the Khadas vendor kernel,
the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows
how to ha
arm64: dts: meson: Describe G12b GPU as coherent
According to a downstream commit I found in the Khadas vendor kernel,
the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows
how to handle this properly) we should describe it as such. Otherwise
the mismatch leads to all manner of fun with mismatched attributes and
inadvertently snooping stale data from caches, which would account for
at least some of the brokenness observed on this platform.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/765446e529e50b304af63432da7836c4d31eb8d4.1600780574.git.robin.murphy@arm.com
show more ...
|
| #
beba2ac6 |
| 22-Sep-2020 |
Robin Murphy <robin.murphy@arm.com> |
arm64: dts: meson: Describe G12b GPU as coherent
commit 03544505cb10ddc73df3b6176e71cdb366834134 upstream.
According to a downstream commit I found in the Khadas vendor kernel,
the GPU on G12b is w
arm64: dts: meson: Describe G12b GPU as coherent
commit 03544505cb10ddc73df3b6176e71cdb366834134 upstream.
According to a downstream commit I found in the Khadas vendor kernel,
the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows
how to handle this properly) we should describe it as such. Otherwise
the mismatch leads to all manner of fun with mismatched attributes and
inadvertently snooping stale data from caches, which would account for
at least some of the brokenness observed on this platform.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/765446e529e50b304af63432da7836c4d31eb8d4.1600780574.git.robin.murphy@arm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41 |
|
| #
fc9eab4b |
| 12-May-2020 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi
The G12B thermal nodes should be in the meson-g12b.dtsi file.
Fixes: 195f140318a9 ("arm64: dts: meson: g12b: add cooling propertie
arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi
The G12B thermal nodes should be in the meson-g12b.dtsi file.
Fixes: 195f140318a9 ("arm64: dts: meson: g12b: add cooling properties")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512093916.19676-2-narmstrong@baylibre.com
show more ...
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|
Revision tags: v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
|
| #
195f1403 |
| 04-Oct-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
arm64: dts: meson: g12b: add cooling properties
Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
arm64: dts: meson: g12b: add cooling properties
Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.3.2, v5.3.1, v5.3 |
|
| #
6eeaf4d2 |
| 13-Sep-2019 |
Frank Hartung <supervisedthinking@gmail.com> |
arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B
Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs
are equal; the A53s cores are weaker than the A72s.
Include
arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B
Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs
are equal; the A53s cores are weaker than the A72s.
Include capacity-dmips-mhz properties to tell the OS there is a difference
in processing capacity. The dmips values are based on similar submissions for
other A53/A72 SoCs: HiSilicon 3660 [1] and Rockchip RK3399 [2].
This change is particularly beneficial for use-cases like retro gaming where
emulators often run on a single core. The OS now chooses an A72 core instead
of an A53 core.
[1] https://lore.kernel.org/patchwork/patch/862742/
[2] https://patchwork.kernel.org/patch/10836577/
Signed-off-by: Frank Hartung <supervisedthinking@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
|
| #
2871626b |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: factor the power domain.
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
Signed-off-by:
arm64: dts: meson: g12: factor the power domain.
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
| #
9ed437d6 |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: add a g12 layer
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dtsi for part whic
arm64: dts: meson: g12: add a g12 layer
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dtsi for part which apply to the g12a and g12b but not the sm1.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.11, v5.2.10 |
|
| #
f4f1c8d9 |
| 23-Aug-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the ri
arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[khilman: minor subject edit: add dts]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.9, v5.2.8, v5.2.7, v5.2.6 |
|
| #
b96d4e92 |
| 31-Jul-2019 |
Christian Hewitt <christianshewitt@gmail.com> |
arm64: dts: meson-g12b: support a311d and s922x cpu operating points
Meson g12b ships with a low-speed (S922X) and high-speed (A311D) variant
so remove cpu_opp_table nodes in meson-g12b.dtsi and cre
arm64: dts: meson-g12b: support a311d and s922x cpu operating points
Meson g12b ships with a low-speed (S922X) and high-speed (A311D) variant
so remove cpu_opp_table nodes in meson-g12b.dtsi and create two new dtsi
that can be included in device-specific dts files. Opp points were taken
from the vendor BSP kernel.
Also make meson-g12b-odroid-n2.dts include the new meson-g12b-s922x.dtsi.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.5 |
|
| #
53fbee33 |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12b: add cpus OPP tables
Add the OPP table taken from the HardKernel Odroid-N2 DTS.
The Amlogic G12B SoC seems to available in 2 types :
- low-speed: Cortex-A73 Cluster up to 1,7
arm64: dts: meson-g12b: add cpus OPP tables
Add the OPP table taken from the HardKernel Odroid-N2 DTS.
The Amlogic G12B SoC seems to available in 2 types :
- low-speed: Cortex-A73 Cluster up to 1,704GHz
- high-speed: Cortex-A73 Cluster up to 2.208GHz
The Cortex-A73 Cluster can be clocked up to 1,896GHz for both types.
The Vendor Amlogic A311D OPP table are slighly different, with lower
voltages than the HardKernel S922X tables but seems to be high-speed type.
This adds the conservative OPP table with the S922X higher voltages
and the maximum low-speed OPP frequency.
The values were tested to be stable on an HardKernel Odroid-N2 board
running the arm64 cpuburn at [1] and cycling between all the possible
cpufreq translations for both clusters and checking the final frequency
using the clock-measurer, script at [2].
[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
| #
1499218c |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
To simplify the representation of differences betweem the G12A and G12B
SoCs, move the common nodes into a meson-g12-common.dtsi fi
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
To simplify the representation of differences betweem the G12A and G12B
SoCs, move the common nodes into a meson-g12-common.dtsi file and
express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi.
This separation will help for DVFS and future Amlogic SM1 Family support.
The sd_emmc_a quirk is added in the g12a/g12b since since it's already
known the sd_emmc_a controller is fixed in the next SM1 SoC family.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7 |
|
| #
c35f6dc5 |
| 03-Jun-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: Add minimal support for Odroid-N2
This patch adds basic support for :
- Amlogic G12B, which is very similar to G12A
- The HardKernel Odroid-N2 based on the S922X SoC
The Amlogic
arm64: dts: meson: Add minimal support for Odroid-N2
This patch adds basic support for :
- Amlogic G12B, which is very similar to G12A
- The HardKernel Odroid-N2 based on the S922X SoC
The Amlogic G12B SoC is very similar with the G12A SoC, sharing
most of the features and architecture, but with these differences :
- The first CPU cluster only has 2xCortex-A53 instead of 4
- G12B has a second cluster of 4xCortex-A73
- Both cluster can achieve 2GHz instead of 1,8GHz for G12A
- CPU Clock architecture is difference, thus needing a different
compatible to handle this slight difference
- Supports a MIPI CSI input
- Embeds a Mali-G52 instead of a Mali-G31, but integration is the same
Actual support is done in the same way as for the GXM support, including
the G12A dtsi and redefining the CPU clusters.
Unlike GXM, the first cluster is different, thus needing to remove
the last 2 cpu nodes of the first cluster.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
[khilman: add vin-supply for vcc_v5 as suggested by Anand Moon]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
beba2ac6 |
| 22-Sep-2020 |
Robin Murphy <robin.murphy@arm.com> |
arm64: dts: meson: Describe G12b GPU as coherent
commit 03544505cb10ddc73df3b6176e71cdb366834134 upstream.
According to a downstream commit I found in the Khadas vendor kernel,
arm64: dts: meson: Describe G12b GPU as coherent
commit 03544505cb10ddc73df3b6176e71cdb366834134 upstream.
According to a downstream commit I found in the Khadas vendor kernel,
the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows
how to handle this properly) we should describe it as such. Otherwise
the mismatch leads to all manner of fun with mismatched attributes and
inadvertently snooping stale data from caches, which would account for
at least some of the brokenness observed on this platform.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/765446e529e50b304af63432da7836c4d31eb8d4.1600780574.git.robin.murphy@arm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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|
Revision tags: v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41 |
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| #
fc9eab4b |
| 12-May-2020 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi
The G12B thermal nodes should be in the meson-g12b.dtsi file.
Fixes: 195f140318a9 ("arm64: dts: meson: g12b: add c
arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi
The G12B thermal nodes should be in the meson-g12b.dtsi file.
Fixes: 195f140318a9 ("arm64: dts: meson: g12b: add cooling properties")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512093916.19676-2-narmstrong@baylibre.com
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|
Revision tags: v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
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| #
195f1403 |
| 04-Oct-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
arm64: dts: meson: g12b: add cooling properties
Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christi
arm64: dts: meson: g12b: add cooling properties
Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v5.3.2, v5.3.1, v5.3 |
|
| #
6eeaf4d2 |
| 13-Sep-2019 |
Frank Hartung <supervisedthinking@gmail.com> |
arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B
Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs
are equal; the A53s cores are weaker than the A7
arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B
Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs
are equal; the A53s cores are weaker than the A72s.
Include capacity-dmips-mhz properties to tell the OS there is a difference
in processing capacity. The dmips values are based on similar submissions for
other A53/A72 SoCs: HiSilicon 3660 [1] and Rockchip RK3399 [2].
This change is particularly beneficial for use-cases like retro gaming where
emulators often run on a single core. The OS now chooses an A72 core instead
of an A53 core.
[1] https://lore.kernel.org/patchwork/patch/862742/
[2] https://patchwork.kernel.org/patch/10836577/
Signed-off-by: Frank Hartung <supervisedthinking@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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|
Revision tags: v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
|
| #
2871626b |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: factor the power domain.
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
arm64: dts: meson: g12: factor the power domain.
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
9ed437d6 |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: add a g12 layer
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dt
arm64: dts: meson: g12: add a g12 layer
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dtsi for part which apply to the g12a and g12b but not the sm1.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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|
Revision tags: v5.2.11, v5.2.10 |
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| #
f4f1c8d9 |
| 23-Aug-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and
arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[khilman: minor subject edit: add dts]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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|
Revision tags: v5.2.9, v5.2.8, v5.2.7, v5.2.6 |
|
| #
b96d4e92 |
| 31-Jul-2019 |
Christian Hewitt <christianshewitt@gmail.com> |
arm64: dts: meson-g12b: support a311d and s922x cpu operating points
Meson g12b ships with a low-speed (S922X) and high-speed (A311D) variant
so remove cpu_opp_table nodes in meson-g12b.
arm64: dts: meson-g12b: support a311d and s922x cpu operating points
Meson g12b ships with a low-speed (S922X) and high-speed (A311D) variant
so remove cpu_opp_table nodes in meson-g12b.dtsi and create two new dtsi
that can be included in device-specific dts files. Opp points were taken
from the vendor BSP kernel.
Also make meson-g12b-odroid-n2.dts include the new meson-g12b-s922x.dtsi.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Revision tags: v5.2.5 |
|
| #
53fbee33 |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12b: add cpus OPP tables
Add the OPP table taken from the HardKernel Odroid-N2 DTS.
The Amlogic G12B SoC seems to available in 2 types :
- low-speed: Cortex-A
arm64: dts: meson-g12b: add cpus OPP tables
Add the OPP table taken from the HardKernel Odroid-N2 DTS.
The Amlogic G12B SoC seems to available in 2 types :
- low-speed: Cortex-A73 Cluster up to 1,704GHz
- high-speed: Cortex-A73 Cluster up to 2.208GHz
The Cortex-A73 Cluster can be clocked up to 1,896GHz for both types.
The Vendor Amlogic A311D OPP table are slighly different, with lower
voltages than the HardKernel S922X tables but seems to be high-speed type.
This adds the conservative OPP table with the S922X higher voltages
and the maximum low-speed OPP frequency.
The values were tested to be stable on an HardKernel Odroid-N2 board
running the arm64 cpuburn at [1] and cycling between all the possible
cpufreq translations for both clusters and checking the final frequency
using the clock-measurer, script at [2].
[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
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