1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include "meson-g12.dtsi"
8
9/ {
10	compatible = "amlogic,g12b";
11
12	cpus {
13		#address-cells = <0x2>;
14		#size-cells = <0x0>;
15
16		cpu-map {
17			cluster0 {
18				core0 {
19					cpu = <&cpu0>;
20				};
21
22				core1 {
23					cpu = <&cpu1>;
24				};
25			};
26
27			cluster1 {
28				core0 {
29					cpu = <&cpu100>;
30				};
31
32				core1 {
33					cpu = <&cpu101>;
34				};
35
36				core2 {
37					cpu = <&cpu102>;
38				};
39
40				core3 {
41					cpu = <&cpu103>;
42				};
43			};
44		};
45
46		cpu0: cpu@0 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a53";
49			reg = <0x0 0x0>;
50			enable-method = "psci";
51			capacity-dmips-mhz = <592>;
52			next-level-cache = <&l2>;
53		};
54
55		cpu1: cpu@1 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			reg = <0x0 0x1>;
59			enable-method = "psci";
60			capacity-dmips-mhz = <592>;
61			next-level-cache = <&l2>;
62		};
63
64		cpu100: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a73";
67			reg = <0x0 0x100>;
68			enable-method = "psci";
69			capacity-dmips-mhz = <1024>;
70			next-level-cache = <&l2>;
71		};
72
73		cpu101: cpu@101 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a73";
76			reg = <0x0 0x101>;
77			enable-method = "psci";
78			capacity-dmips-mhz = <1024>;
79			next-level-cache = <&l2>;
80		};
81
82		cpu102: cpu@102 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a73";
85			reg = <0x0 0x102>;
86			enable-method = "psci";
87			capacity-dmips-mhz = <1024>;
88			next-level-cache = <&l2>;
89		};
90
91		cpu103: cpu@103 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a73";
94			reg = <0x0 0x103>;
95			enable-method = "psci";
96			capacity-dmips-mhz = <1024>;
97			next-level-cache = <&l2>;
98		};
99
100		l2: l2-cache0 {
101			compatible = "cache";
102		};
103	};
104};
105
106&clkc {
107	compatible = "amlogic,g12b-clkc";
108};
109
110