1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include "meson-g12.dtsi"
8
9/ {
10	compatible = "amlogic,g12b";
11
12	cpus {
13		#address-cells = <0x2>;
14		#size-cells = <0x0>;
15
16		cpu-map {
17			cluster0 {
18				core0 {
19					cpu = <&cpu0>;
20				};
21
22				core1 {
23					cpu = <&cpu1>;
24				};
25			};
26
27			cluster1 {
28				core0 {
29					cpu = <&cpu100>;
30				};
31
32				core1 {
33					cpu = <&cpu101>;
34				};
35
36				core2 {
37					cpu = <&cpu102>;
38				};
39
40				core3 {
41					cpu = <&cpu103>;
42				};
43			};
44		};
45
46		cpu0: cpu@0 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a53";
49			reg = <0x0 0x0>;
50			enable-method = "psci";
51			next-level-cache = <&l2>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a53";
57			reg = <0x0 0x1>;
58			enable-method = "psci";
59			next-level-cache = <&l2>;
60		};
61
62		cpu100: cpu@100 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a73";
65			reg = <0x0 0x100>;
66			enable-method = "psci";
67			next-level-cache = <&l2>;
68		};
69
70		cpu101: cpu@101 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a73";
73			reg = <0x0 0x101>;
74			enable-method = "psci";
75			next-level-cache = <&l2>;
76		};
77
78		cpu102: cpu@102 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a73";
81			reg = <0x0 0x102>;
82			enable-method = "psci";
83			next-level-cache = <&l2>;
84		};
85
86		cpu103: cpu@103 {
87			device_type = "cpu";
88			compatible = "arm,cortex-a73";
89			reg = <0x0 0x103>;
90			enable-method = "psci";
91			next-level-cache = <&l2>;
92		};
93
94		l2: l2-cache0 {
95			compatible = "cache";
96		};
97	};
98};
99
100&clkc {
101	compatible = "amlogic,g12b-clkc";
102};
103
104