media: ccs-pll: Initialise best_div to avoid a compiler warning

Initialise best_div local variable to avoid a compiler warning. The
warning was harmless though.

Reported-by: Hans Verkuil <hverkuil-

media: ccs-pll: Initialise best_div to avoid a compiler warning

Initialise best_div local variable to avoid a compiler warning. The
warning was harmless though.

Reported-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

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media: Revert "media: ccs-pll: Fix MODULE_LICENSE"

This reverts commit b3c0115e34adcabe12fce8845e24ca6f04c1554e.

As per Documentation/process/license-rules.rst "GPL v2" exists only for
historical r

media: Revert "media: ccs-pll: Fix MODULE_LICENSE"

This reverts commit b3c0115e34adcabe12fce8845e24ca6f04c1554e.

As per Documentation/process/license-rules.rst "GPL v2" exists only for
historical reasons and has the same meaning as "GPL". So revert this
patch.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Switch from standard integer types to kernel ones

The preferred integer types in the kernel are the Linux specific ones,
switch from standard C types to u32 and alike.

The patch has

media: ccs-pll: Switch from standard integer types to kernel ones

The preferred integer types in the kernel are the Linux specific ones,
switch from standard C types to u32 and alike.

The patch has been produced with the following Coccinelle spatch, with few
alignment adjustments:

@@
typedef uint32_t;
typedef u32;
@@
- uint32_t
+ u32

@@
typedef uint16_t;
typedef u16;
@@
- uint16_t
+ u16

@@
typedef uint8_t;
typedef u8;
@@
- uint8_t
+ u8

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Fix link frequency for C-PHY

The highest fundamental frequency signal for C-PHY is half of the symbol
rate which is similar to D-PHY. Take this into account in ccs-pll.

Also remove

media: ccs-pll: Fix link frequency for C-PHY

The highest fundamental frequency signal for C-PHY is half of the symbol
rate which is similar to D-PHY. Take this into account in ccs-pll.

Also remove the outdated comment.

Fixes: 8030aa4f9c51 ("media: ccs-pll: Add C-PHY support")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Print pixel rates

Print pixel rates on CSI-2 bus as well as in pixel array as the variation
allowed in PLL capabilities makes this non-trivial to figure out
otherwise.

Signed-off-by

media: ccs-pll: Print pixel rates

Print pixel rates on CSI-2 bus as well as in pixel array as the variation
allowed in PLL capabilities makes this non-trivial to figure out
otherwise.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add support for DDR OP system and pixel clocks

Add support for dual data rate operational system and pixel clocks. This
is implemented using two PLL flags.

Signed-off-by: Sakari Ail

media: ccs-pll: Add support for DDR OP system and pixel clocks

Add support for dual data rate operational system and pixel clocks. This
is implemented using two PLL flags.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs: Dual PLL support

Add support for sensors that either require dual PLL or support single or
dual PLL but use dual PLL as default.

Use sensor default configuration for sensors that suppor

media: ccs: Dual PLL support

Add support for sensors that either require dual PLL or support single or
dual PLL but use dual PLL as default.

Use sensor default configuration for sensors that support both modes.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add trivial dual PLL support

Add support for sensors that have separate VT and OP domain PLLs.

This support is trivial in the sense that it aims for the same VT pixel
rate than that

media: ccs-pll: Add trivial dual PLL support

Add support for sensors that have separate VT and OP domain PLLs.

This support is trivial in the sense that it aims for the same VT pixel
rate than that on the CSI-2 bus. The vast majority of sensors is better
supported by higher frequencies in VT domain in binned and possibly scaled
configurations.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Separate VT divisor limit calculation from the rest

Separate VT divisor limit calculation from the rest of the VT PLL branch
calculation. This way it can be used for dual PLL support

media: ccs-pll: Separate VT divisor limit calculation from the rest

Separate VT divisor limit calculation from the rest of the VT PLL branch
calculation. This way it can be used for dual PLL support as well.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Fix VT post-PLL divisor calculation

The PLL calculator only searched even total divisor values apart from one,
but this is wrong: the total divisor is odd in cases where system divis

media: ccs-pll: Fix VT post-PLL divisor calculation

The PLL calculator only searched even total divisor values apart from one,
but this is wrong: the total divisor is odd in cases where system divisor
is one. Fix this by including odd total PLL values where system divisor is
one to the search.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Make VT divisors 16-bit

Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after
all.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro

media: ccs-pll: Make VT divisors 16-bit

Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after
all.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Rework bounds checks

Refactor bounds checks so that the caller can decide what to check. This
allows doing the checks early, when the values are available.

This also adds front OP P

media: ccs-pll: Rework bounds checks

Refactor bounds checks so that the caller can decide what to check. This
allows doing the checks early, when the values are available.

This also adds front OP PLL configuration and limits.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Print relevant information on PLL tree

Print information on PLL tree configuration based on the flags. This also
adds support for printing dual PLL trees, and better separates betwee

media: ccs-pll: Print relevant information on PLL tree

Print information on PLL tree configuration based on the flags. This also
adds support for printing dual PLL trees, and better separates between OP
and VT PLL trees.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Better separate OP and VT sub-tree calculation

Better separate OP PLL branch calculation from VT branch calculation.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signe

media: ccs-pll: Better separate OP and VT sub-tree calculation

Better separate OP PLL branch calculation from VT branch calculation.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Check for derating and overrating, support non-derating sensors

Some sensors support derating (VT domain speed faster than OP) or
overrating (VT domain speed slower than OP). While t

media: ccs-pll: Check for derating and overrating, support non-derating sensors

Some sensors support derating (VT domain speed faster than OP) or
overrating (VT domain speed slower than OP). While this was supported for
the driver, the hardware support for the feature was never verified. Do
that now, and for those devices without that support, VT and OP speeds
have to match.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Split off VT subtree calculation

Split off the VT sub clock tree calculation from the rest, into its own
function. Also call the op_pll_fr argument pll_fr, since soon these may
not b

media: ccs-pll: Split off VT subtree calculation

Split off the VT sub clock tree calculation from the rest, into its own
function. Also call the op_pll_fr argument pll_fr, since soon these may
not be OP tree values.

This paves way for additional features in the future such as dual PLL
support.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add C-PHY support

Add C-PHY support for the CCS PLL calculator.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kerne

media: ccs-pll: Add C-PHY support

Add C-PHY support for the CCS PLL calculator.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add sanity checks

Add sanity checks for fields that could cause division by zero.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mc

media: ccs-pll: Add sanity checks

Add sanity checks for fields that could cause division by zero.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add support flexible OP PLL pixel clock divider

Flexible OP PLL pixel clock divider allows a higher OP pixel clock than
what the bus can transfer. This generally makes it easier to s

media: ccs-pll: Add support flexible OP PLL pixel clock divider

Flexible OP PLL pixel clock divider allows a higher OP pixel clock than
what the bus can transfer. This generally makes it easier to select pixel
clock dividers.

This changes how the pixel rate on the bus and minimum VT divisor are
calculated, as the pixel rate is no longer directly determined by the
OP pixel clock and the number of the lanes.

Also add a sanity check for sensors that do not support flexible OP PLL
pixel clock divider. This could have caused the PLL calculator to come up
with an invalid configuration for those devices.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Support two cycles per pixel on OP domain

The l parameter defines the number of clock cycles to process a single
pixel per OP lane. It is calculated based on a new register
op_bits_p

media: ccs-pll: Support two cycles per pixel on OP domain

The l parameter defines the number of clock cycles to process a single
pixel per OP lane. It is calculated based on a new register
op_bits_per_lane.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add support for extended input PLL clock divider

CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculat

media: ccs-pll: Add support for extended input PLL clock divider

CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculator and the CCS
driver.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add support for decoupled OP domain calculation

Add support for decoupled OP domain clock calculation. This means that the
number of VT and OP domain clocks are no longer dependent o

media: ccs-pll: Add support for decoupled OP domain calculation

Add support for decoupled OP domain clock calculation. This means that the
number of VT and OP domain clocks are no longer dependent on the number of
CSI-2 lanes in the lane speed mode.

The support also replaces the existing quirk flag to calculate OP domain
clocks per lane.

Also support decoupled OP domain calculation in the CCS driver.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Add support for lane speed model

CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.

Move calculation of the pixel rate on the

media: ccs-pll: Add support for lane speed model

CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.

Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Use explicit 32-bit unsigned type

Use uint32_t instead of unsigned int for a variable that contains
explicitly 32-bit numbers.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.

media: ccs-pll: Use explicit 32-bit unsigned type

Use uint32_t instead of unsigned int for a variable that contains
explicitly 32-bit numbers.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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media: ccs-pll: Fix check for PLL multiplier upper bound

The additional multiplier (for higher VT timing) of the PLL multiplier was
checked against the upper limit but the result was rounded up, pos

media: ccs-pll: Fix check for PLL multiplier upper bound

The additional multiplier (for higher VT timing) of the PLL multiplier was
checked against the upper limit but the result was rounded up, possibly
producing too high additional multiplier. Round down instead to keep
within hardware limits.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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