1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/media/i2c/ccs-pll.c 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2011--2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12 #include <linux/device.h> 13 #include <linux/gcd.h> 14 #include <linux/lcm.h> 15 #include <linux/module.h> 16 17 #include "ccs-pll.h" 18 19 /* Return an even number or one. */ 20 static inline uint32_t clk_div_even(uint32_t a) 21 { 22 return max_t(uint32_t, 1, a & ~1); 23 } 24 25 /* Return an even number or one. */ 26 static inline uint32_t clk_div_even_up(uint32_t a) 27 { 28 if (a == 1) 29 return 1; 30 return (a + 1) & ~1; 31 } 32 33 static inline uint32_t is_one_or_even(uint32_t a) 34 { 35 if (a == 1) 36 return 1; 37 if (a & 1) 38 return 0; 39 40 return 1; 41 } 42 43 static inline uint32_t one_or_more(uint32_t a) 44 { 45 return a ?: 1; 46 } 47 48 static int bounds_check(struct device *dev, uint32_t val, 49 uint32_t min, uint32_t max, char *str) 50 { 51 if (val >= min && val <= max) 52 return 0; 53 54 dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max); 55 56 return -EINVAL; 57 } 58 59 static void print_pll(struct device *dev, struct ccs_pll *pll) 60 { 61 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->vt_fr.pre_pll_clk_div); 62 dev_dbg(dev, "pll_multiplier \t%u\n", pll->vt_fr.pll_multiplier); 63 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { 64 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_bk.sys_clk_div); 65 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_bk.pix_clk_div); 66 } 67 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_bk.sys_clk_div); 68 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_bk.pix_clk_div); 69 70 dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); 71 dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->vt_fr.pll_ip_clk_freq_hz); 72 dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->vt_fr.pll_op_clk_freq_hz); 73 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { 74 dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", 75 pll->op_bk.sys_clk_freq_hz); 76 dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", 77 pll->op_bk.pix_clk_freq_hz); 78 } 79 dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_bk.sys_clk_freq_hz); 80 dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_bk.pix_clk_freq_hz); 81 } 82 83 static int check_all_bounds(struct device *dev, 84 const struct ccs_pll_limits *lim, 85 const struct ccs_pll_branch_limits_fr *op_lim_fr, 86 const struct ccs_pll_branch_limits_bk *op_lim_bk, 87 struct ccs_pll *pll, 88 struct ccs_pll_branch_fr *op_pll_fr, 89 struct ccs_pll_branch_bk *op_pll_bk) 90 { 91 int rval; 92 93 rval = bounds_check(dev, op_pll_fr->pll_ip_clk_freq_hz, 94 op_lim_fr->min_pll_ip_clk_freq_hz, 95 op_lim_fr->max_pll_ip_clk_freq_hz, 96 "pll_ip_clk_freq_hz"); 97 if (!rval) 98 rval = bounds_check( 99 dev, op_pll_fr->pll_multiplier, 100 op_lim_fr->min_pll_multiplier, 101 op_lim_fr->max_pll_multiplier, "pll_multiplier"); 102 if (!rval) 103 rval = bounds_check( 104 dev, op_pll_fr->pll_op_clk_freq_hz, 105 op_lim_fr->min_pll_op_clk_freq_hz, 106 op_lim_fr->max_pll_op_clk_freq_hz, "pll_op_clk_freq_hz"); 107 if (!rval) 108 rval = bounds_check( 109 dev, op_pll_bk->sys_clk_div, 110 op_lim_bk->min_sys_clk_div, op_lim_bk->max_sys_clk_div, 111 "op_sys_clk_div"); 112 if (!rval) 113 rval = bounds_check( 114 dev, op_pll_bk->sys_clk_freq_hz, 115 op_lim_bk->min_sys_clk_freq_hz, 116 op_lim_bk->max_sys_clk_freq_hz, 117 "op_sys_clk_freq_hz"); 118 if (!rval) 119 rval = bounds_check( 120 dev, op_pll_bk->pix_clk_freq_hz, 121 op_lim_bk->min_pix_clk_freq_hz, 122 op_lim_bk->max_pix_clk_freq_hz, 123 "op_pix_clk_freq_hz"); 124 125 /* 126 * If there are no OP clocks, the VT clocks are contained in 127 * the OP clock struct. 128 */ 129 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) 130 return rval; 131 132 if (!rval) 133 rval = bounds_check( 134 dev, pll->vt_bk.sys_clk_freq_hz, 135 lim->vt_bk.min_sys_clk_freq_hz, 136 lim->vt_bk.max_sys_clk_freq_hz, 137 "vt_sys_clk_freq_hz"); 138 if (!rval) 139 rval = bounds_check( 140 dev, pll->vt_bk.pix_clk_freq_hz, 141 lim->vt_bk.min_pix_clk_freq_hz, 142 lim->vt_bk.max_pix_clk_freq_hz, 143 "vt_pix_clk_freq_hz"); 144 145 return rval; 146 } 147 148 /* 149 * Heuristically guess the PLL tree for a given common multiplier and 150 * divisor. Begin with the operational timing and continue to video 151 * timing once operational timing has been verified. 152 * 153 * @mul is the PLL multiplier and @div is the common divisor 154 * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL 155 * multiplier will be a multiple of @mul. 156 * 157 * @return Zero on success, error code on error. 158 */ 159 static int 160 __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 161 const struct ccs_pll_branch_limits_fr *op_lim_fr, 162 const struct ccs_pll_branch_limits_bk *op_lim_bk, 163 struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, 164 struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, 165 uint32_t div, uint32_t lane_op_clock_ratio) 166 { 167 uint32_t sys_div; 168 uint32_t best_pix_div = INT_MAX >> 1; 169 uint32_t vt_op_binning_div; 170 /* 171 * Higher multipliers (and divisors) are often required than 172 * necessitated by the external clock and the output clocks. 173 * There are limits for all values in the clock tree. These 174 * are the minimum and maximum multiplier for mul. 175 */ 176 uint32_t more_mul_min, more_mul_max; 177 uint32_t more_mul_factor; 178 uint32_t min_vt_div, max_vt_div, vt_div; 179 uint32_t min_sys_div, max_sys_div; 180 uint32_t i; 181 182 /* 183 * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be 184 * too high. 185 */ 186 dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); 187 188 /* Don't go above max pll multiplier. */ 189 more_mul_max = op_lim_fr->max_pll_multiplier / mul; 190 dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", 191 more_mul_max); 192 /* Don't go above max pll op frequency. */ 193 more_mul_max = 194 min_t(uint32_t, 195 more_mul_max, 196 op_lim_fr->max_pll_op_clk_freq_hz 197 / (pll->ext_clk_freq_hz / op_pll_fr->pre_pll_clk_div * mul)); 198 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", 199 more_mul_max); 200 /* Don't go above the division capability of op sys clock divider. */ 201 more_mul_max = min(more_mul_max, 202 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div 203 / div); 204 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", 205 more_mul_max); 206 /* Ensure we won't go above max_pll_multiplier. */ 207 more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); 208 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", 209 more_mul_max); 210 211 /* Ensure we won't go below min_pll_op_clk_freq_hz. */ 212 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, 213 pll->ext_clk_freq_hz / 214 op_pll_fr->pre_pll_clk_div * mul); 215 dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", 216 more_mul_min); 217 /* Ensure we won't go below min_pll_multiplier. */ 218 more_mul_min = max(more_mul_min, 219 DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); 220 dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", 221 more_mul_min); 222 223 if (more_mul_min > more_mul_max) { 224 dev_dbg(dev, 225 "unable to compute more_mul_min and more_mul_max\n"); 226 return -EINVAL; 227 } 228 229 more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; 230 dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); 231 more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); 232 dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", 233 more_mul_factor); 234 i = roundup(more_mul_min, more_mul_factor); 235 if (!is_one_or_even(i)) 236 i <<= 1; 237 238 dev_dbg(dev, "final more_mul: %u\n", i); 239 if (i > more_mul_max) { 240 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); 241 return -EINVAL; 242 } 243 244 op_pll_fr->pll_multiplier = mul * i; 245 op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; 246 dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); 247 248 op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz 249 / op_pll_fr->pre_pll_clk_div; 250 251 op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz 252 * op_pll_fr->pll_multiplier; 253 254 op_pll_bk->pix_clk_div = pll->bits_per_pixel; 255 dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); 256 257 op_pll_bk->pix_clk_freq_hz = 258 op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; 259 260 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { 261 /* No OP clocks --- VT clocks are used instead. */ 262 goto out_skip_vt_calc; 263 } 264 265 /* 266 * Some sensors perform analogue binning and some do this 267 * digitally. The ones doing this digitally can be roughly be 268 * found out using this formula. The ones doing this digitally 269 * should run at higher clock rate, so smaller divisor is used 270 * on video timing side. 271 */ 272 if (lim->min_line_length_pck_bin > lim->min_line_length_pck 273 / pll->binning_horizontal) 274 vt_op_binning_div = pll->binning_horizontal; 275 else 276 vt_op_binning_div = 1; 277 dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); 278 279 /* 280 * Profile 2 supports vt_pix_clk_div E [4, 10] 281 * 282 * Horizontal binning can be used as a base for difference in 283 * divisors. One must make sure that horizontal blanking is 284 * enough to accommodate the CSI-2 sync codes. 285 * 286 * Take scaling factor into account as well. 287 * 288 * Find absolute limits for the factor of vt divider. 289 */ 290 dev_dbg(dev, "scale_m: %u\n", pll->scale_m); 291 min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div 292 * op_pll_bk->sys_clk_div * pll->scale_n, 293 lane_op_clock_ratio * vt_op_binning_div 294 * pll->scale_m); 295 296 /* Find smallest and biggest allowed vt divisor. */ 297 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); 298 min_vt_div = max(min_vt_div, 299 DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, 300 lim->vt_bk.max_pix_clk_freq_hz)); 301 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", 302 min_vt_div); 303 min_vt_div = max_t(uint32_t, min_vt_div, 304 lim->vt_bk.min_pix_clk_div 305 * lim->vt_bk.min_sys_clk_div); 306 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); 307 308 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; 309 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); 310 max_vt_div = min(max_vt_div, 311 DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, 312 lim->vt_bk.min_pix_clk_freq_hz)); 313 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", 314 max_vt_div); 315 316 /* 317 * Find limitsits for sys_clk_div. Not all values are possible 318 * with all values of pix_clk_div. 319 */ 320 min_sys_div = lim->vt_bk.min_sys_clk_div; 321 dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); 322 min_sys_div = max(min_sys_div, 323 DIV_ROUND_UP(min_vt_div, 324 lim->vt_bk.max_pix_clk_div)); 325 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); 326 min_sys_div = max(min_sys_div, 327 op_pll_fr->pll_op_clk_freq_hz 328 / lim->vt_bk.max_sys_clk_freq_hz); 329 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); 330 min_sys_div = clk_div_even_up(min_sys_div); 331 dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); 332 333 max_sys_div = lim->vt_bk.max_sys_clk_div; 334 dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); 335 max_sys_div = min(max_sys_div, 336 DIV_ROUND_UP(max_vt_div, 337 lim->vt_bk.min_pix_clk_div)); 338 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); 339 max_sys_div = min(max_sys_div, 340 DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, 341 lim->vt_bk.min_pix_clk_freq_hz)); 342 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); 343 344 /* 345 * Find pix_div such that a legal pix_div * sys_div results 346 * into a value which is not smaller than div, the desired 347 * divisor. 348 */ 349 for (vt_div = min_vt_div; vt_div <= max_vt_div; 350 vt_div += 2 - (vt_div & 1)) { 351 for (sys_div = min_sys_div; 352 sys_div <= max_sys_div; 353 sys_div += 2 - (sys_div & 1)) { 354 uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); 355 uint16_t rounded_div; 356 357 if (pix_div < lim->vt_bk.min_pix_clk_div 358 || pix_div > lim->vt_bk.max_pix_clk_div) { 359 dev_dbg(dev, 360 "pix_div %u too small or too big (%u--%u)\n", 361 pix_div, 362 lim->vt_bk.min_pix_clk_div, 363 lim->vt_bk.max_pix_clk_div); 364 continue; 365 } 366 367 rounded_div = roundup(vt_div, best_pix_div); 368 369 /* Check if this one is better. */ 370 if (pix_div * sys_div <= rounded_div) 371 best_pix_div = pix_div; 372 373 /* Bail out if we've already found the best value. */ 374 if (vt_div == rounded_div) 375 break; 376 } 377 if (best_pix_div < INT_MAX >> 1) 378 break; 379 } 380 381 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div); 382 pll->vt_bk.pix_clk_div = best_pix_div; 383 384 pll->vt_bk.sys_clk_freq_hz = 385 op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; 386 pll->vt_bk.pix_clk_freq_hz = 387 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; 388 389 out_skip_vt_calc: 390 pll->pixel_rate_csi = 391 op_pll_bk->pix_clk_freq_hz * lane_op_clock_ratio; 392 pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz; 393 394 return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr, 395 op_pll_bk); 396 } 397 398 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 399 struct ccs_pll *pll) 400 { 401 const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr; 402 const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; 403 struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; 404 struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; 405 uint16_t min_op_pre_pll_clk_div; 406 uint16_t max_op_pre_pll_clk_div; 407 uint32_t lane_op_clock_ratio; 408 uint32_t mul, div; 409 uint32_t i; 410 int rval = -EINVAL; 411 412 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { 413 /* 414 * If there's no OP PLL at all, use the VT values 415 * instead. The OP values are ignored for the rest of 416 * the PLL calculation. 417 */ 418 op_lim_fr = &lim->vt_fr; 419 op_lim_bk = &lim->vt_bk; 420 op_pll_bk = &pll->vt_bk; 421 } 422 423 if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) 424 lane_op_clock_ratio = pll->csi2.lanes; 425 else 426 lane_op_clock_ratio = 1; 427 dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio); 428 429 dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, 430 pll->binning_vertical); 431 432 switch (pll->bus_type) { 433 case CCS_PLL_BUS_TYPE_CSI2_DPHY: 434 /* CSI transfers 2 bits per clock per lane; thus times 2 */ 435 op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 436 * (pll->csi2.lanes / lane_op_clock_ratio); 437 break; 438 default: 439 return -EINVAL; 440 } 441 442 /* Figure out limits for OP pre-pll divider based on extclk */ 443 dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", 444 op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); 445 max_op_pre_pll_clk_div = 446 min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div, 447 clk_div_even(pll->ext_clk_freq_hz / 448 op_lim_fr->min_pll_ip_clk_freq_hz)); 449 min_op_pre_pll_clk_div = 450 max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div, 451 clk_div_even_up( 452 DIV_ROUND_UP(pll->ext_clk_freq_hz, 453 op_lim_fr->max_pll_ip_clk_freq_hz))); 454 dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", 455 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 456 457 i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz); 458 mul = op_pll_bk->sys_clk_freq_hz / i; 459 div = pll->ext_clk_freq_hz / i; 460 dev_dbg(dev, "mul %u / div %u\n", mul, div); 461 462 min_op_pre_pll_clk_div = 463 max_t(uint16_t, min_op_pre_pll_clk_div, 464 clk_div_even_up( 465 mul / 466 one_or_more( 467 DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz, 468 pll->ext_clk_freq_hz)))); 469 dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", 470 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 471 472 for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div; 473 op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; 474 op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) { 475 rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, 476 op_pll_fr, op_pll_bk, mul, div, 477 lane_op_clock_ratio); 478 if (rval) 479 continue; 480 481 print_pll(dev, pll); 482 return 0; 483 } 484 485 dev_dbg(dev, "unable to compute pre_pll divisor\n"); 486 487 return rval; 488 } 489 EXPORT_SYMBOL_GPL(ccs_pll_calculate); 490 491 MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>"); 492 MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); 493 MODULE_LICENSE("GPL v2"); 494