1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/media/i2c/ccs-pll.c 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2011--2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12 #include <linux/device.h> 13 #include <linux/gcd.h> 14 #include <linux/lcm.h> 15 #include <linux/module.h> 16 17 #include "ccs-pll.h" 18 19 /* Return an even number or one. */ 20 static inline uint32_t clk_div_even(uint32_t a) 21 { 22 return max_t(uint32_t, 1, a & ~1); 23 } 24 25 /* Return an even number or one. */ 26 static inline uint32_t clk_div_even_up(uint32_t a) 27 { 28 if (a == 1) 29 return 1; 30 return (a + 1) & ~1; 31 } 32 33 static inline uint32_t is_one_or_even(uint32_t a) 34 { 35 if (a == 1) 36 return 1; 37 if (a & 1) 38 return 0; 39 40 return 1; 41 } 42 43 static inline uint32_t one_or_more(uint32_t a) 44 { 45 return a ?: 1; 46 } 47 48 static int bounds_check(struct device *dev, uint32_t val, 49 uint32_t min, uint32_t max, char *str) 50 { 51 if (val >= min && val <= max) 52 return 0; 53 54 dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max); 55 56 return -EINVAL; 57 } 58 59 static void print_pll(struct device *dev, struct ccs_pll *pll) 60 { 61 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->vt_fr.pre_pll_clk_div); 62 dev_dbg(dev, "pll_multiplier \t%u\n", pll->vt_fr.pll_multiplier); 63 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { 64 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_bk.sys_clk_div); 65 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_bk.pix_clk_div); 66 } 67 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_bk.sys_clk_div); 68 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_bk.pix_clk_div); 69 70 dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); 71 dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->vt_fr.pll_ip_clk_freq_hz); 72 dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->vt_fr.pll_op_clk_freq_hz); 73 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { 74 dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", 75 pll->op_bk.sys_clk_freq_hz); 76 dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", 77 pll->op_bk.pix_clk_freq_hz); 78 } 79 dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_bk.sys_clk_freq_hz); 80 dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_bk.pix_clk_freq_hz); 81 } 82 83 static int check_all_bounds(struct device *dev, 84 const struct ccs_pll_limits *lim, 85 const struct ccs_pll_branch_limits_fr *op_lim_fr, 86 const struct ccs_pll_branch_limits_bk *op_lim_bk, 87 struct ccs_pll *pll, 88 struct ccs_pll_branch_fr *op_pll_fr, 89 struct ccs_pll_branch_bk *op_pll_bk) 90 { 91 int rval; 92 93 rval = bounds_check(dev, op_pll_fr->pll_ip_clk_freq_hz, 94 op_lim_fr->min_pll_ip_clk_freq_hz, 95 op_lim_fr->max_pll_ip_clk_freq_hz, 96 "pll_ip_clk_freq_hz"); 97 if (!rval) 98 rval = bounds_check( 99 dev, op_pll_fr->pll_multiplier, 100 op_lim_fr->min_pll_multiplier, 101 op_lim_fr->max_pll_multiplier, "pll_multiplier"); 102 if (!rval) 103 rval = bounds_check( 104 dev, op_pll_fr->pll_op_clk_freq_hz, 105 op_lim_fr->min_pll_op_clk_freq_hz, 106 op_lim_fr->max_pll_op_clk_freq_hz, "pll_op_clk_freq_hz"); 107 if (!rval) 108 rval = bounds_check( 109 dev, op_pll_bk->sys_clk_div, 110 op_lim_bk->min_sys_clk_div, op_lim_bk->max_sys_clk_div, 111 "op_sys_clk_div"); 112 if (!rval) 113 rval = bounds_check( 114 dev, op_pll_bk->sys_clk_freq_hz, 115 op_lim_bk->min_sys_clk_freq_hz, 116 op_lim_bk->max_sys_clk_freq_hz, 117 "op_sys_clk_freq_hz"); 118 if (!rval) 119 rval = bounds_check( 120 dev, op_pll_bk->pix_clk_freq_hz, 121 op_lim_bk->min_pix_clk_freq_hz, 122 op_lim_bk->max_pix_clk_freq_hz, 123 "op_pix_clk_freq_hz"); 124 125 /* 126 * If there are no OP clocks, the VT clocks are contained in 127 * the OP clock struct. 128 */ 129 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) 130 return rval; 131 132 if (!rval) 133 rval = bounds_check( 134 dev, pll->vt_bk.sys_clk_freq_hz, 135 lim->vt_bk.min_sys_clk_freq_hz, 136 lim->vt_bk.max_sys_clk_freq_hz, 137 "vt_sys_clk_freq_hz"); 138 if (!rval) 139 rval = bounds_check( 140 dev, pll->vt_bk.pix_clk_freq_hz, 141 lim->vt_bk.min_pix_clk_freq_hz, 142 lim->vt_bk.max_pix_clk_freq_hz, 143 "vt_pix_clk_freq_hz"); 144 145 return rval; 146 } 147 148 /* 149 * Heuristically guess the PLL tree for a given common multiplier and 150 * divisor. Begin with the operational timing and continue to video 151 * timing once operational timing has been verified. 152 * 153 * @mul is the PLL multiplier and @div is the common divisor 154 * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL 155 * multiplier will be a multiple of @mul. 156 * 157 * @return Zero on success, error code on error. 158 */ 159 static int 160 __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 161 const struct ccs_pll_branch_limits_fr *op_lim_fr, 162 const struct ccs_pll_branch_limits_bk *op_lim_bk, 163 struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, 164 struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, 165 uint32_t div, uint32_t l) 166 { 167 uint32_t sys_div; 168 uint32_t best_pix_div = INT_MAX >> 1; 169 uint32_t vt_op_binning_div; 170 /* 171 * Higher multipliers (and divisors) are often required than 172 * necessitated by the external clock and the output clocks. 173 * There are limits for all values in the clock tree. These 174 * are the minimum and maximum multiplier for mul. 175 */ 176 uint32_t more_mul_min, more_mul_max; 177 uint32_t more_mul_factor; 178 uint32_t min_vt_div, max_vt_div, vt_div; 179 uint32_t min_sys_div, max_sys_div; 180 uint32_t i; 181 182 /* 183 * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be 184 * too high. 185 */ 186 dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); 187 188 /* Don't go above max pll multiplier. */ 189 more_mul_max = op_lim_fr->max_pll_multiplier / mul; 190 dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", 191 more_mul_max); 192 /* Don't go above max pll op frequency. */ 193 more_mul_max = 194 min_t(uint32_t, 195 more_mul_max, 196 op_lim_fr->max_pll_op_clk_freq_hz 197 / (pll->ext_clk_freq_hz / 198 op_pll_fr->pre_pll_clk_div * mul)); 199 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", 200 more_mul_max); 201 /* Don't go above the division capability of op sys clock divider. */ 202 more_mul_max = min(more_mul_max, 203 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div 204 / div); 205 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", 206 more_mul_max); 207 /* Ensure we won't go above max_pll_multiplier. */ 208 more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); 209 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", 210 more_mul_max); 211 212 /* Ensure we won't go below min_pll_op_clk_freq_hz. */ 213 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, 214 pll->ext_clk_freq_hz / 215 op_pll_fr->pre_pll_clk_div * mul); 216 dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", 217 more_mul_min); 218 /* Ensure we won't go below min_pll_multiplier. */ 219 more_mul_min = max(more_mul_min, 220 DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); 221 dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", 222 more_mul_min); 223 224 if (more_mul_min > more_mul_max) { 225 dev_dbg(dev, 226 "unable to compute more_mul_min and more_mul_max\n"); 227 return -EINVAL; 228 } 229 230 more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; 231 dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); 232 more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); 233 dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", 234 more_mul_factor); 235 i = roundup(more_mul_min, more_mul_factor); 236 if (!is_one_or_even(i)) 237 i <<= 1; 238 239 dev_dbg(dev, "final more_mul: %u\n", i); 240 if (i > more_mul_max) { 241 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); 242 return -EINVAL; 243 } 244 245 op_pll_fr->pll_multiplier = mul * i; 246 op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; 247 dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); 248 249 op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz 250 / op_pll_fr->pre_pll_clk_div; 251 252 op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz 253 * op_pll_fr->pll_multiplier; 254 255 if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) 256 op_pll_bk->pix_clk_div = pll->bits_per_pixel 257 * pll->op_lanes / pll->csi2.lanes / l; 258 else 259 op_pll_bk->pix_clk_div = pll->bits_per_pixel / l; 260 261 op_pll_bk->pix_clk_freq_hz = 262 op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; 263 264 dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); 265 266 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { 267 /* No OP clocks --- VT clocks are used instead. */ 268 goto out_skip_vt_calc; 269 } 270 271 /* 272 * Some sensors perform analogue binning and some do this 273 * digitally. The ones doing this digitally can be roughly be 274 * found out using this formula. The ones doing this digitally 275 * should run at higher clock rate, so smaller divisor is used 276 * on video timing side. 277 */ 278 if (lim->min_line_length_pck_bin > lim->min_line_length_pck 279 / pll->binning_horizontal) 280 vt_op_binning_div = pll->binning_horizontal; 281 else 282 vt_op_binning_div = 1; 283 dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); 284 285 /* 286 * Profile 2 supports vt_pix_clk_div E [4, 10] 287 * 288 * Horizontal binning can be used as a base for difference in 289 * divisors. One must make sure that horizontal blanking is 290 * enough to accommodate the CSI-2 sync codes. 291 * 292 * Take scaling factor and number of VT lanes into account as well. 293 * 294 * Find absolute limits for the factor of vt divider. 295 */ 296 dev_dbg(dev, "scale_m: %u\n", pll->scale_m); 297 min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div 298 * pll->scale_n * pll->vt_lanes, 299 (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 300 pll->csi2.lanes : 1) 301 * vt_op_binning_div * pll->scale_m); 302 303 /* Find smallest and biggest allowed vt divisor. */ 304 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); 305 min_vt_div = max(min_vt_div, 306 DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, 307 lim->vt_bk.max_pix_clk_freq_hz)); 308 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", 309 min_vt_div); 310 min_vt_div = max_t(uint32_t, min_vt_div, 311 lim->vt_bk.min_pix_clk_div 312 * lim->vt_bk.min_sys_clk_div); 313 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); 314 315 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; 316 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); 317 max_vt_div = min(max_vt_div, 318 DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, 319 lim->vt_bk.min_pix_clk_freq_hz)); 320 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", 321 max_vt_div); 322 323 /* 324 * Find limitsits for sys_clk_div. Not all values are possible 325 * with all values of pix_clk_div. 326 */ 327 min_sys_div = lim->vt_bk.min_sys_clk_div; 328 dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); 329 min_sys_div = max(min_sys_div, 330 DIV_ROUND_UP(min_vt_div, 331 lim->vt_bk.max_pix_clk_div)); 332 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); 333 min_sys_div = max(min_sys_div, 334 op_pll_fr->pll_op_clk_freq_hz 335 / lim->vt_bk.max_sys_clk_freq_hz); 336 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); 337 min_sys_div = clk_div_even_up(min_sys_div); 338 dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); 339 340 max_sys_div = lim->vt_bk.max_sys_clk_div; 341 dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); 342 max_sys_div = min(max_sys_div, 343 DIV_ROUND_UP(max_vt_div, 344 lim->vt_bk.min_pix_clk_div)); 345 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); 346 max_sys_div = min(max_sys_div, 347 DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, 348 lim->vt_bk.min_pix_clk_freq_hz)); 349 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); 350 351 /* 352 * Find pix_div such that a legal pix_div * sys_div results 353 * into a value which is not smaller than div, the desired 354 * divisor. 355 */ 356 for (vt_div = min_vt_div; vt_div <= max_vt_div; 357 vt_div += 2 - (vt_div & 1)) { 358 for (sys_div = min_sys_div; 359 sys_div <= max_sys_div; 360 sys_div += 2 - (sys_div & 1)) { 361 uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); 362 uint16_t rounded_div; 363 364 if (pix_div < lim->vt_bk.min_pix_clk_div 365 || pix_div > lim->vt_bk.max_pix_clk_div) { 366 dev_dbg(dev, 367 "pix_div %u too small or too big (%u--%u)\n", 368 pix_div, 369 lim->vt_bk.min_pix_clk_div, 370 lim->vt_bk.max_pix_clk_div); 371 continue; 372 } 373 374 rounded_div = roundup(vt_div, best_pix_div); 375 376 /* Check if this one is better. */ 377 if (pix_div * sys_div <= rounded_div) 378 best_pix_div = pix_div; 379 380 /* Bail out if we've already found the best value. */ 381 if (vt_div == rounded_div) 382 break; 383 } 384 if (best_pix_div < INT_MAX >> 1) 385 break; 386 } 387 388 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div); 389 pll->vt_bk.pix_clk_div = best_pix_div; 390 391 pll->vt_bk.sys_clk_freq_hz = 392 op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; 393 pll->vt_bk.pix_clk_freq_hz = 394 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; 395 396 out_skip_vt_calc: 397 pll->pixel_rate_pixel_array = 398 pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; 399 400 return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr, 401 op_pll_bk); 402 } 403 404 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 405 struct ccs_pll *pll) 406 { 407 const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr; 408 const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; 409 struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; 410 struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; 411 uint16_t min_op_pre_pll_clk_div; 412 uint16_t max_op_pre_pll_clk_div; 413 uint32_t mul, div; 414 uint32_t l = (!pll->op_bits_per_lane || 415 pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2; 416 uint32_t i; 417 int rval = -EINVAL; 418 419 if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) { 420 pll->op_lanes = 1; 421 pll->vt_lanes = 1; 422 } 423 424 /* 425 * Make sure op_pix_clk_div will be integer --- unless flexible 426 * op_pix_clk_div is supported 427 */ 428 if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) && 429 (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) { 430 dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n", 431 pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l); 432 return -EINVAL; 433 } 434 435 dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes); 436 dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes); 437 438 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { 439 /* 440 * If there's no OP PLL at all, use the VT values 441 * instead. The OP values are ignored for the rest of 442 * the PLL calculation. 443 */ 444 op_lim_fr = &lim->vt_fr; 445 op_lim_bk = &lim->vt_bk; 446 op_pll_bk = &pll->vt_bk; 447 } 448 449 dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, 450 pll->binning_vertical); 451 452 switch (pll->bus_type) { 453 case CCS_PLL_BUS_TYPE_CSI2_DPHY: 454 /* CSI transfers 2 bits per clock per lane; thus times 2 */ 455 op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 456 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 457 1 : pll->csi2.lanes); 458 break; 459 default: 460 return -EINVAL; 461 } 462 463 pll->pixel_rate_csi = 464 op_pll_bk->sys_clk_freq_hz 465 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 466 pll->csi2.lanes : 1) / pll->bits_per_pixel / l; 467 468 /* Figure out limits for OP pre-pll divider based on extclk */ 469 dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", 470 op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); 471 max_op_pre_pll_clk_div = 472 min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div, 473 clk_div_even(pll->ext_clk_freq_hz / 474 op_lim_fr->min_pll_ip_clk_freq_hz)); 475 min_op_pre_pll_clk_div = 476 max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div, 477 clk_div_even_up( 478 DIV_ROUND_UP(pll->ext_clk_freq_hz, 479 op_lim_fr->max_pll_ip_clk_freq_hz))); 480 dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", 481 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 482 483 i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz); 484 mul = op_pll_bk->sys_clk_freq_hz / i; 485 div = pll->ext_clk_freq_hz / i; 486 dev_dbg(dev, "mul %u / div %u\n", mul, div); 487 488 min_op_pre_pll_clk_div = 489 max_t(uint16_t, min_op_pre_pll_clk_div, 490 clk_div_even_up( 491 mul / 492 one_or_more( 493 DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz, 494 pll->ext_clk_freq_hz)))); 495 dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", 496 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 497 498 for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div; 499 op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; 500 op_pll_fr->pre_pll_clk_div += 501 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 502 2 - (op_pll_fr->pre_pll_clk_div & 1)) { 503 rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, 504 op_pll_fr, op_pll_bk, mul, div, l); 505 if (rval) 506 continue; 507 508 print_pll(dev, pll); 509 return 0; 510 } 511 512 dev_dbg(dev, "unable to compute pre_pll divisor\n"); 513 514 return rval; 515 } 516 EXPORT_SYMBOL_GPL(ccs_pll_calculate); 517 518 MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>"); 519 MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); 520 MODULE_LICENSE("GPL v2"); 521