Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53 |
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#
f0dce5c4 |
| 02-Jul-2022 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Use the highest possible DMA burst size
Until now, when running at the maximum resolution of 1280x720 at 32bpp on the JZ4770 SoC the output was garbled, the X/Y position of the top-left
drm/ingenic: Use the highest possible DMA burst size
Until now, when running at the maximum resolution of 1280x720 at 32bpp on the JZ4770 SoC the output was garbled, the X/Y position of the top-left corner of the framebuffer warping to a random position with the whole image being offset accordingly, every time a new frame was being submitted.
This problem can be eliminated by using a bigger burst size for the DMA.
Set in each soc_info structure the maximum burst size supported by the corresponding SoC, and use it in the driver.
Set the new value using regmap_update_bits() instead of regmap_set_bits(), since we do want to override the old value of the burst size. (Note that regmap_set_bits() wasn't really valid before for the same reason, but it never seemed to be a problem).
Cc: <stable@vger.kernel.org> Fixes: 90b86fcc47b4 ("DRM: Add KMS driver for the Ingenic JZ47xx SoCs") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://patchwork.freedesktop.org/patch/msgid/20220702230727.66704-1-paul@crapouillou.net Acked-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Christophe Branchereau <cbranchereau@gmail.com>
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Revision tags: v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7 |
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b807fd2c |
| 02-Dec-2021 |
Paul Boddie <paul@boddie.org.uk> |
drm/ingenic: Add support for JZ4780 and HDMI output
Add support for the LCD controller present on JZ4780 SoCs. This SoC uses 8-byte descriptors which extend the current 4-byte descriptors used for o
drm/ingenic: Add support for JZ4780 and HDMI output
Add support for the LCD controller present on JZ4780 SoCs. This SoC uses 8-byte descriptors which extend the current 4-byte descriptors used for other Ingenic SoCs.
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://patchwork.freedesktop.org/patch/msgid/caf9e56b64b0717563e03172b30fa03736e92e15.1638470392.git.hns@goldelico.com
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Revision tags: v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40 |
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4a791cb6 |
| 23-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add option to alloc cached GEM buffers
Alloc GEM buffers backed by noncoherent memory on SoCs where it is actually faster than write-combine.
This dramatically speeds up software rende
drm/ingenic: Add option to alloc cached GEM buffers
Alloc GEM buffers backed by noncoherent memory on SoCs where it is actually faster than write-combine.
This dramatically speeds up software rendering on these SoCs, even for tasks where write-combine memory should in theory be faster (e.g. simple blits).
v3: The option is now selected per-SoC instead of being a module parameter.
v5: - Fix drm_atomic_get_new_plane_state() used to retrieve the old state - Use custom drm_gem_fb_create() - Only check damage clips and sync DMA buffers if non-coherent buffers are used
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210523170415.90410-4-paul@crapouillou.net
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Revision tags: v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
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ca459a74 |
| 19-Nov-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for serial 8-bit delta-RGB panels
Add support for 24-bit panels that are connected through a 8-bit bus and use delta-RGB, which means a RGB pixel ordering on odd lines, and
drm/ingenic: Add support for serial 8-bit delta-RGB panels
Add support for 24-bit panels that are connected through a 8-bit bus and use delta-RGB, which means a RGB pixel ordering on odd lines, and a GBR pixel ordering on even lines.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20201119155559.14112-4-paul@crapouillou.net
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14 |
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21271d41 |
| 04-Oct-2020 |
Paul Cercueil <paul@crapouillou.net> |
Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"
This reverts commit 37054fc81443 ("gpu/drm: ingenic: Add option to mmap GEM buffers cached")
At the very moment this commit was crea
Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"
This reverts commit 37054fc81443 ("gpu/drm: ingenic: Add option to mmap GEM buffers cached")
At the very moment this commit was created, the DMA API it relied on was modified in the DMA tree, which caused the driver to break in linux-next.
Revert it for now, and it will be resubmitted later to work with the new DMA API.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20201004141758.1013317-1-paul@crapouillou.net
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Revision tags: v5.8.13 |
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dba09e83 |
| 26-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for 24-bit modes
Starting from the JZ4725B SoC, the primary and overlay planes support 24-bit pixel modes (8 bits per color component, without dummy byte). Add support for t
drm/ingenic: Add support for 24-bit modes
Starting from the JZ4725B SoC, the primary and overlay planes support 24-bit pixel modes (8 bits per color component, without dummy byte). Add support for these in the ingenic-drm driver.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200926170501.1109197-8-paul@crapouillou.net
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bb857605 |
| 26-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for 30-bit modes
Starting from the JZ4760 SoC, the primary and overlay planes support 30-bit pixel modes (10 bits per color component). Add support for these in the ingenic-
drm/ingenic: Add support for 30-bit modes
Starting from the JZ4760 SoC, the primary and overlay planes support 30-bit pixel modes (10 bits per color component). Add support for these in the ingenic-drm driver.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200926170501.1109197-7-paul@crapouillou.net
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a3fb64c0 |
| 04-Oct-2020 |
Paul Cercueil <paul@crapouillou.net> |
Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"
This reverts commit 37054fc81443 ("gpu/drm: ingenic: Add option to mmap GEM buffers cached")
At the very moment this commit was crea
Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"
This reverts commit 37054fc81443 ("gpu/drm: ingenic: Add option to mmap GEM buffers cached")
At the very moment this commit was created, the DMA API it relied on was modified in the DMA tree, which caused the driver to break in linux-next.
Revert it for now, and it will be resubmitted later to work with the new DMA API.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20201004141758.1013317-1-paul@crapouillou.net
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Revision tags: v5.8.12, v5.8.11, v5.8.10 |
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#
37054fc8 |
| 12-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
gpu/drm: ingenic: Add option to mmap GEM buffers cached
Ingenic SoCs are most notably used in cheap chinese handheld gaming consoles. There, the games and applications generally render in software d
gpu/drm: ingenic: Add option to mmap GEM buffers cached
Ingenic SoCs are most notably used in cheap chinese handheld gaming consoles. There, the games and applications generally render in software directly into GEM buffers.
Traditionally, GEM buffers are mapped write-combine. Writes to the buffer are accelerated, and reads are slow. Application doing lots of alpha-blending paint inside shadow buffers, which is then memcpy'd into the final GEM buffer.
On recent Ingenic SoCs however, it is much faster to have a fully cached GEM buffer, in which applications paint directly, and whose data is invalidated before scanout, than having a write-combine GEM buffer, even when alpha blending is not used.
Add an optional 'cached_gem_buffers' parameter to the ingenic-drm driver to allow GEM buffers to be mapped fully-cached, in order to speed up software rendering.
v2: Use standard noncoherent DMA APIs
v3: Use damage clips instead of invalidating full frames
v4: Avoid dma_pgprot() which is not exported. Using vm_get_page_prot() is enough in this case.
v5: - Avoid calling drm_gem_cma_prime_mmap(). It has the side effect that an extra object reference is obtained, which causes our dumb buffers to never be freed. It should have been drm_gem_cma_mmap_obj(). However, our custom mmap function only differs with one flag, so we can cleanly handle both modes in ingenic_drm_gem_mmap(). - Call drm_gem_vm_close() if drm_mmap_attrs() failed, just like in drm_gem_cma_mmap_obj().
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200912195639.176001-1-paul@crapouillou.net
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Revision tags: v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53 |
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fc1acf31 |
| 16-Jul-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for the IPU
Add support for the Image Processing Unit (IPU) found in all Ingenic SoCs.
The IPU can upscale and downscale a source frame of arbitrary size ranging from 4x4 t
drm/ingenic: Add support for the IPU
Add support for the Image Processing Unit (IPU) found in all Ingenic SoCs.
The IPU can upscale and downscale a source frame of arbitrary size ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering on newer SoCs, bilinear filtering on older SoCs. Nearest-neighbour can also be obtained with proper coefficients.
Starting from the JZ4725B, the IPU supports a mode where its output is sent directly to the LCDC, without having to be written to RAM first. This makes it possible to use the IPU as a DRM plane on the compatible SoCs, and have it convert and scale anything the userspace asks for to what's available for the display.
Regarding pixel formats, older SoCs support packed YUV 4:2:2 and various planar YUV formats. Newer SoCs introduced support for RGB.
Since the IPU is a separate hardware block, to make it work properly the Ingenic DRM driver will now register itself as a component master in case the IPU driver has been enabled in the config.
When enabled in the config, the CRTC will see the IPU as a second primary plane. It cannot be enabled at the same time as the regular primary plane. It has the same priority, which means that it will also display below the overlay plane.
v2: - ingenic-ipu is no longer its own module. It will be built into the ingenic-drm module. - If enabled in the config, both the core driver and the IPU driver will register as components; otherwise the core driver will bypass that and call the ingenic_drm_bind() function directly. - Since both files now build into the same module, the symbols previously exported as GPL are not exported anymore, since they are only used internally. - Fix SPDX license header in ingenic-ipu.h - Avoid using 'for(;;);' loops without trailing statement(s)
v3: - Pass priv structure to IRQ handler; that way we don't hardcode the expectation that the IPU plane is at index #0. - Rework osd_changed() to account for src_* changes - Add multiplanar YUV 4:4:4 support - Commit fb addresses to HW at vblank, since addr registers are not shadow registers - Probe IPU component later so that IPU plane is last - Fix driver not working on IPU-less hardware - Use IPU driver's name as the IRQ name to avoid having two 'ingenic-drm' in /proc/interrupts - Fix IPU only working for still images on JZ4725B - Add a bit more code comments
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-10-paul@crapouillou.net
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3c9bea4e |
| 16-Jul-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for OSD mode
All Ingenic SoCs starting from the JZ4725B support OSD mode.
In this mode, two separate planes can be used. They can have different positions and sizes, and on
drm/ingenic: Add support for OSD mode
All Ingenic SoCs starting from the JZ4725B support OSD mode.
In this mode, two separate planes can be used. They can have different positions and sizes, and one can be overlayed on top of the other.
v2: Use fallthrough; instead of /* fall-through */
v3: - Add custom atomic_tail function to handle case where HW gives no VBLANK - Use regmap_set_bits() / regmap_clear_bits() when possible - Use dma_hwdesc_f{0,1} fields in priv structure instead of array - Use dmam_alloc_coherent() instead of dma_alloc_coherent() - Use more meaningful 0xf0 / 0xf1 values as DMA descriptors IDs - Add a bit more code comments
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-9-paul@crapouillou.net
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4b11cb7f |
| 16-Jul-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Move register definitions to ingenic-drm.h
Move the register definitions to ingenic-drm.h, to keep ingenic-drm-drv.c tidy.
v2: Fix SPDX license tag v3: No change
Signed-off-by: Paul C
drm/ingenic: Move register definitions to ingenic-drm.h
Move the register definitions to ingenic-drm.h, to keep ingenic-drm-drv.c tidy.
v2: Fix SPDX license tag v3: No change
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-7-paul@crapouillou.net
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Revision tags: v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53 |
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fc1acf31 |
| 16-Jul-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for the IPU Add support for the Image Processing Unit (IPU) found in all Ingenic SoCs. The IPU can upscale and downscale a source frame of arbitrary siz
drm/ingenic: Add support for the IPU Add support for the Image Processing Unit (IPU) found in all Ingenic SoCs. The IPU can upscale and downscale a source frame of arbitrary size ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering on newer SoCs, bilinear filtering on older SoCs. Nearest-neighbour can also be obtained with proper coefficients. Starting from the JZ4725B, the IPU supports a mode where its output is sent directly to the LCDC, without having to be written to RAM first. This makes it possible to use the IPU as a DRM plane on the compatible SoCs, and have it convert and scale anything the userspace asks for to what's available for the display. Regarding pixel formats, older SoCs support packed YUV 4:2:2 and various planar YUV formats. Newer SoCs introduced support for RGB. Since the IPU is a separate hardware block, to make it work properly the Ingenic DRM driver will now register itself as a component master in case the IPU driver has been enabled in the config. When enabled in the config, the CRTC will see the IPU as a second primary plane. It cannot be enabled at the same time as the regular primary plane. It has the same priority, which means that it will also display below the overlay plane. v2: - ingenic-ipu is no longer its own module. It will be built into the ingenic-drm module. - If enabled in the config, both the core driver and the IPU driver will register as components; otherwise the core driver will bypass that and call the ingenic_drm_bind() function directly. - Since both files now build into the same module, the symbols previously exported as GPL are not exported anymore, since they are only used internally. - Fix SPDX license header in ingenic-ipu.h - Avoid using 'for(;;);' loops without trailing statement(s) v3: - Pass priv structure to IRQ handler; that way we don't hardcode the expectation that the IPU plane is at index #0. - Rework osd_changed() to account for src_* changes - Add multiplanar YUV 4:4:4 support - Commit fb addresses to HW at vblank, since addr registers are not shadow registers - Probe IPU component later so that IPU plane is last - Fix driver not working on IPU-less hardware - Use IPU driver's name as the IRQ name to avoid having two 'ingenic-drm' in /proc/interrupts - Fix IPU only working for still images on JZ4725B - Add a bit more code comments Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-10-paul@crapouillou.net
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#
3c9bea4e |
| 16-Jul-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Add support for OSD mode All Ingenic SoCs starting from the JZ4725B support OSD mode. In this mode, two separate planes can be used. They can have different positio
drm/ingenic: Add support for OSD mode All Ingenic SoCs starting from the JZ4725B support OSD mode. In this mode, two separate planes can be used. They can have different positions and sizes, and one can be overlayed on top of the other. v2: Use fallthrough; instead of /* fall-through */ v3: - Add custom atomic_tail function to handle case where HW gives no VBLANK - Use regmap_set_bits() / regmap_clear_bits() when possible - Use dma_hwdesc_f{0,1} fields in priv structure instead of array - Use dmam_alloc_coherent() instead of dma_alloc_coherent() - Use more meaningful 0xf0 / 0xf1 values as DMA descriptors IDs - Add a bit more code comments Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-9-paul@crapouillou.net
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#
4b11cb7f |
| 16-Jul-2020 |
Paul Cercueil <paul@crapouillou.net> |
drm/ingenic: Move register definitions to ingenic-drm.h Move the register definitions to ingenic-drm.h, to keep ingenic-drm-drv.c tidy. v2: Fix SPDX license tag v3: No chang
drm/ingenic: Move register definitions to ingenic-drm.h Move the register definitions to ingenic-drm.h, to keep ingenic-drm-drv.c tidy. v2: Fix SPDX license tag v3: No change Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-7-paul@crapouillou.net
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