1 /* SPDX-License-Identifier: GPL-2.0 */
2 //
3 // Ingenic JZ47xx KMS driver - Register definitions and private API
4 //
5 // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
6 
7 #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
8 #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
9 
10 #include <linux/bitops.h>
11 #include <linux/types.h>
12 
13 #define JZ_REG_LCD_CFG				0x00
14 #define JZ_REG_LCD_VSYNC			0x04
15 #define JZ_REG_LCD_HSYNC			0x08
16 #define JZ_REG_LCD_VAT				0x0C
17 #define JZ_REG_LCD_DAH				0x10
18 #define JZ_REG_LCD_DAV				0x14
19 #define JZ_REG_LCD_PS				0x18
20 #define JZ_REG_LCD_CLS				0x1C
21 #define JZ_REG_LCD_SPL				0x20
22 #define JZ_REG_LCD_REV				0x24
23 #define JZ_REG_LCD_CTRL				0x30
24 #define JZ_REG_LCD_STATE			0x34
25 #define JZ_REG_LCD_IID				0x38
26 #define JZ_REG_LCD_DA0				0x40
27 #define JZ_REG_LCD_SA0				0x44
28 #define JZ_REG_LCD_FID0				0x48
29 #define JZ_REG_LCD_CMD0				0x4C
30 #define JZ_REG_LCD_DA1				0x50
31 #define JZ_REG_LCD_SA1				0x54
32 #define JZ_REG_LCD_FID1				0x58
33 #define JZ_REG_LCD_CMD1				0x5C
34 #define JZ_REG_LCD_OSDC				0x100
35 #define JZ_REG_LCD_OSDCTRL			0x104
36 #define JZ_REG_LCD_OSDS				0x108
37 #define JZ_REG_LCD_BGC				0x10c
38 #define JZ_REG_LCD_KEY0				0x110
39 #define JZ_REG_LCD_KEY1				0x114
40 #define JZ_REG_LCD_ALPHA			0x118
41 #define JZ_REG_LCD_IPUR				0x11c
42 #define JZ_REG_LCD_XYP0				0x120
43 #define JZ_REG_LCD_XYP1				0x124
44 #define JZ_REG_LCD_SIZE0			0x128
45 #define JZ_REG_LCD_SIZE1			0x12c
46 
47 #define JZ_LCD_CFG_SLCD				BIT(31)
48 #define JZ_LCD_CFG_PS_DISABLE			BIT(23)
49 #define JZ_LCD_CFG_CLS_DISABLE			BIT(22)
50 #define JZ_LCD_CFG_SPL_DISABLE			BIT(21)
51 #define JZ_LCD_CFG_REV_DISABLE			BIT(20)
52 #define JZ_LCD_CFG_HSYNCM			BIT(19)
53 #define JZ_LCD_CFG_PCLKM			BIT(18)
54 #define JZ_LCD_CFG_INV				BIT(17)
55 #define JZ_LCD_CFG_SYNC_DIR			BIT(16)
56 #define JZ_LCD_CFG_PS_POLARITY			BIT(15)
57 #define JZ_LCD_CFG_CLS_POLARITY			BIT(14)
58 #define JZ_LCD_CFG_SPL_POLARITY			BIT(13)
59 #define JZ_LCD_CFG_REV_POLARITY			BIT(12)
60 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW		BIT(11)
61 #define JZ_LCD_CFG_PCLK_FALLING_EDGE		BIT(10)
62 #define JZ_LCD_CFG_DE_ACTIVE_LOW		BIT(9)
63 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW		BIT(8)
64 #define JZ_LCD_CFG_18_BIT			BIT(7)
65 #define JZ_LCD_CFG_PDW				(BIT(5) | BIT(4))
66 
67 #define JZ_LCD_CFG_MODE_GENERIC_16BIT		0
68 #define JZ_LCD_CFG_MODE_GENERIC_18BIT		BIT(7)
69 #define JZ_LCD_CFG_MODE_GENERIC_24BIT		BIT(6)
70 
71 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1		1
72 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2		2
73 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3		3
74 
75 #define JZ_LCD_CFG_MODE_TV_OUT_P		4
76 #define JZ_LCD_CFG_MODE_TV_OUT_I		6
77 
78 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN	8
79 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN	9
80 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN		10
81 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN	11
82 
83 #define JZ_LCD_CFG_MODE_8BIT_SERIAL		12
84 #define JZ_LCD_CFG_MODE_LCM			13
85 
86 #define JZ_LCD_VSYNC_VPS_OFFSET			16
87 #define JZ_LCD_VSYNC_VPE_OFFSET			0
88 
89 #define JZ_LCD_HSYNC_HPS_OFFSET			16
90 #define JZ_LCD_HSYNC_HPE_OFFSET			0
91 
92 #define JZ_LCD_VAT_HT_OFFSET			16
93 #define JZ_LCD_VAT_VT_OFFSET			0
94 
95 #define JZ_LCD_DAH_HDS_OFFSET			16
96 #define JZ_LCD_DAH_HDE_OFFSET			0
97 
98 #define JZ_LCD_DAV_VDS_OFFSET			16
99 #define JZ_LCD_DAV_VDE_OFFSET			0
100 
101 #define JZ_LCD_CTRL_BURST_4			(0x0 << 28)
102 #define JZ_LCD_CTRL_BURST_8			(0x1 << 28)
103 #define JZ_LCD_CTRL_BURST_16			(0x2 << 28)
104 #define JZ_LCD_CTRL_RGB555			BIT(27)
105 #define JZ_LCD_CTRL_OFUP			BIT(26)
106 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16		(0x0 << 24)
107 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4		(0x1 << 24)
108 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2		(0x2 << 24)
109 #define JZ_LCD_CTRL_PDD_MASK			(0xff << 16)
110 #define JZ_LCD_CTRL_EOF_IRQ			BIT(13)
111 #define JZ_LCD_CTRL_SOF_IRQ			BIT(12)
112 #define JZ_LCD_CTRL_OFU_IRQ			BIT(11)
113 #define JZ_LCD_CTRL_IFU0_IRQ			BIT(10)
114 #define JZ_LCD_CTRL_IFU1_IRQ			BIT(9)
115 #define JZ_LCD_CTRL_DD_IRQ			BIT(8)
116 #define JZ_LCD_CTRL_QDD_IRQ			BIT(7)
117 #define JZ_LCD_CTRL_REVERSE_ENDIAN		BIT(6)
118 #define JZ_LCD_CTRL_LSB_FISRT			BIT(5)
119 #define JZ_LCD_CTRL_DISABLE			BIT(4)
120 #define JZ_LCD_CTRL_ENABLE			BIT(3)
121 #define JZ_LCD_CTRL_BPP_1			0x0
122 #define JZ_LCD_CTRL_BPP_2			0x1
123 #define JZ_LCD_CTRL_BPP_4			0x2
124 #define JZ_LCD_CTRL_BPP_8			0x3
125 #define JZ_LCD_CTRL_BPP_15_16			0x4
126 #define JZ_LCD_CTRL_BPP_18_24			0x5
127 #define JZ_LCD_CTRL_BPP_24_COMP			0x6
128 #define JZ_LCD_CTRL_BPP_30			0x7
129 #define JZ_LCD_CTRL_BPP_MASK			(JZ_LCD_CTRL_RGB555 | 0x7)
130 
131 #define JZ_LCD_CMD_SOF_IRQ			BIT(31)
132 #define JZ_LCD_CMD_EOF_IRQ			BIT(30)
133 #define JZ_LCD_CMD_ENABLE_PAL			BIT(28)
134 
135 #define JZ_LCD_SYNC_MASK			0x3ff
136 
137 #define JZ_LCD_STATE_EOF_IRQ			BIT(5)
138 #define JZ_LCD_STATE_SOF_IRQ			BIT(4)
139 #define JZ_LCD_STATE_DISABLED			BIT(0)
140 
141 #define JZ_LCD_OSDC_OSDEN			BIT(0)
142 #define JZ_LCD_OSDC_F0EN			BIT(3)
143 #define JZ_LCD_OSDC_F1EN			BIT(4)
144 
145 #define JZ_LCD_OSDCTRL_IPU			BIT(15)
146 #define JZ_LCD_OSDCTRL_RGB555			BIT(4)
147 #define JZ_LCD_OSDCTRL_CHANGE			BIT(3)
148 #define JZ_LCD_OSDCTRL_BPP_15_16		0x4
149 #define JZ_LCD_OSDCTRL_BPP_18_24		0x5
150 #define JZ_LCD_OSDCTRL_BPP_24_COMP		0x6
151 #define JZ_LCD_OSDCTRL_BPP_30			0x7
152 #define JZ_LCD_OSDCTRL_BPP_MASK			(JZ_LCD_OSDCTRL_RGB555 | 0x7)
153 
154 #define JZ_LCD_OSDS_READY			BIT(0)
155 
156 #define JZ_LCD_IPUR_IPUREN			BIT(31)
157 #define JZ_LCD_IPUR_IPUR_LSB			0
158 
159 #define JZ_LCD_XYP01_XPOS_LSB			0
160 #define JZ_LCD_XYP01_YPOS_LSB			16
161 
162 #define JZ_LCD_SIZE01_WIDTH_LSB			0
163 #define JZ_LCD_SIZE01_HEIGHT_LSB		16
164 
165 struct device;
166 struct drm_plane;
167 struct drm_plane_state;
168 struct platform_driver;
169 
170 void ingenic_drm_plane_config(struct device *dev,
171 			      struct drm_plane *plane, u32 fourcc);
172 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane);
173 
174 extern struct platform_driver *ingenic_ipu_driver_ptr;
175 
176 #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */
177