1 /* SPDX-License-Identifier: GPL-2.0 */
2 //
3 // Ingenic JZ47xx KMS driver - Register definitions and private API
4 //
5 // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
6 
7 #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
8 #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
9 
10 #include <linux/bitops.h>
11 
12 #define JZ_REG_LCD_CFG				0x00
13 #define JZ_REG_LCD_VSYNC			0x04
14 #define JZ_REG_LCD_HSYNC			0x08
15 #define JZ_REG_LCD_VAT				0x0C
16 #define JZ_REG_LCD_DAH				0x10
17 #define JZ_REG_LCD_DAV				0x14
18 #define JZ_REG_LCD_PS				0x18
19 #define JZ_REG_LCD_CLS				0x1C
20 #define JZ_REG_LCD_SPL				0x20
21 #define JZ_REG_LCD_REV				0x24
22 #define JZ_REG_LCD_CTRL				0x30
23 #define JZ_REG_LCD_STATE			0x34
24 #define JZ_REG_LCD_IID				0x38
25 #define JZ_REG_LCD_DA0				0x40
26 #define JZ_REG_LCD_SA0				0x44
27 #define JZ_REG_LCD_FID0				0x48
28 #define JZ_REG_LCD_CMD0				0x4C
29 #define JZ_REG_LCD_DA1				0x50
30 #define JZ_REG_LCD_SA1				0x54
31 #define JZ_REG_LCD_FID1				0x58
32 #define JZ_REG_LCD_CMD1				0x5C
33 
34 #define JZ_LCD_CFG_SLCD				BIT(31)
35 #define JZ_LCD_CFG_PS_DISABLE			BIT(23)
36 #define JZ_LCD_CFG_CLS_DISABLE			BIT(22)
37 #define JZ_LCD_CFG_SPL_DISABLE			BIT(21)
38 #define JZ_LCD_CFG_REV_DISABLE			BIT(20)
39 #define JZ_LCD_CFG_HSYNCM			BIT(19)
40 #define JZ_LCD_CFG_PCLKM			BIT(18)
41 #define JZ_LCD_CFG_INV				BIT(17)
42 #define JZ_LCD_CFG_SYNC_DIR			BIT(16)
43 #define JZ_LCD_CFG_PS_POLARITY			BIT(15)
44 #define JZ_LCD_CFG_CLS_POLARITY			BIT(14)
45 #define JZ_LCD_CFG_SPL_POLARITY			BIT(13)
46 #define JZ_LCD_CFG_REV_POLARITY			BIT(12)
47 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW		BIT(11)
48 #define JZ_LCD_CFG_PCLK_FALLING_EDGE		BIT(10)
49 #define JZ_LCD_CFG_DE_ACTIVE_LOW		BIT(9)
50 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW		BIT(8)
51 #define JZ_LCD_CFG_18_BIT			BIT(7)
52 #define JZ_LCD_CFG_PDW				(BIT(5) | BIT(4))
53 
54 #define JZ_LCD_CFG_MODE_GENERIC_16BIT		0
55 #define JZ_LCD_CFG_MODE_GENERIC_18BIT		BIT(7)
56 #define JZ_LCD_CFG_MODE_GENERIC_24BIT		BIT(6)
57 
58 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1		1
59 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2		2
60 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3		3
61 
62 #define JZ_LCD_CFG_MODE_TV_OUT_P		4
63 #define JZ_LCD_CFG_MODE_TV_OUT_I		6
64 
65 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN	8
66 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN	9
67 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN		10
68 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN	11
69 
70 #define JZ_LCD_CFG_MODE_8BIT_SERIAL		12
71 #define JZ_LCD_CFG_MODE_LCM			13
72 
73 #define JZ_LCD_VSYNC_VPS_OFFSET			16
74 #define JZ_LCD_VSYNC_VPE_OFFSET			0
75 
76 #define JZ_LCD_HSYNC_HPS_OFFSET			16
77 #define JZ_LCD_HSYNC_HPE_OFFSET			0
78 
79 #define JZ_LCD_VAT_HT_OFFSET			16
80 #define JZ_LCD_VAT_VT_OFFSET			0
81 
82 #define JZ_LCD_DAH_HDS_OFFSET			16
83 #define JZ_LCD_DAH_HDE_OFFSET			0
84 
85 #define JZ_LCD_DAV_VDS_OFFSET			16
86 #define JZ_LCD_DAV_VDE_OFFSET			0
87 
88 #define JZ_LCD_CTRL_BURST_4			(0x0 << 28)
89 #define JZ_LCD_CTRL_BURST_8			(0x1 << 28)
90 #define JZ_LCD_CTRL_BURST_16			(0x2 << 28)
91 #define JZ_LCD_CTRL_RGB555			BIT(27)
92 #define JZ_LCD_CTRL_OFUP			BIT(26)
93 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16		(0x0 << 24)
94 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4		(0x1 << 24)
95 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2		(0x2 << 24)
96 #define JZ_LCD_CTRL_PDD_MASK			(0xff << 16)
97 #define JZ_LCD_CTRL_EOF_IRQ			BIT(13)
98 #define JZ_LCD_CTRL_SOF_IRQ			BIT(12)
99 #define JZ_LCD_CTRL_OFU_IRQ			BIT(11)
100 #define JZ_LCD_CTRL_IFU0_IRQ			BIT(10)
101 #define JZ_LCD_CTRL_IFU1_IRQ			BIT(9)
102 #define JZ_LCD_CTRL_DD_IRQ			BIT(8)
103 #define JZ_LCD_CTRL_QDD_IRQ			BIT(7)
104 #define JZ_LCD_CTRL_REVERSE_ENDIAN		BIT(6)
105 #define JZ_LCD_CTRL_LSB_FISRT			BIT(5)
106 #define JZ_LCD_CTRL_DISABLE			BIT(4)
107 #define JZ_LCD_CTRL_ENABLE			BIT(3)
108 #define JZ_LCD_CTRL_BPP_1			0x0
109 #define JZ_LCD_CTRL_BPP_2			0x1
110 #define JZ_LCD_CTRL_BPP_4			0x2
111 #define JZ_LCD_CTRL_BPP_8			0x3
112 #define JZ_LCD_CTRL_BPP_15_16			0x4
113 #define JZ_LCD_CTRL_BPP_18_24			0x5
114 #define JZ_LCD_CTRL_BPP_MASK			(JZ_LCD_CTRL_RGB555 | 0x7)
115 
116 #define JZ_LCD_CMD_SOF_IRQ			BIT(31)
117 #define JZ_LCD_CMD_EOF_IRQ			BIT(30)
118 #define JZ_LCD_CMD_ENABLE_PAL			BIT(28)
119 
120 #define JZ_LCD_SYNC_MASK			0x3ff
121 
122 #define JZ_LCD_STATE_EOF_IRQ			BIT(5)
123 #define JZ_LCD_STATE_SOF_IRQ			BIT(4)
124 #define JZ_LCD_STATE_DISABLED			BIT(0)
125 
126 #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */
127