Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31 |
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#
064329c5 |
| 24-May-2023 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: expose swctf threshold setting for legacy powerplay
Preparation for coming optimization which eliminates the influence of GPU temperature momentary fluctuation.
Signed-off-by: Evan Quan
drm/amd/pm: expose swctf threshold setting for legacy powerplay
Preparation for coming optimization which eliminates the influence of GPU temperature momentary fluctuation.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13 |
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#
c3ed0e72 |
| 21-Feb-2023 |
Kun Liu <Kun.Liu2@amd.com> |
drm/amdgpu: added a sysfs interface for thermal throttling
added a sysfs interface for thermal throttling, then userspace can get/update thermal limit
Signed-off-by: Kun Liu <Kun.Liu2@amd.com> Revi
drm/amdgpu: added a sysfs interface for thermal throttling
added a sysfs interface for thermal throttling, then userspace can get/update thermal limit
Signed-off-by: Kun Liu <Kun.Liu2@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.2, v6.1.12 |
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#
230dd6bb |
| 09-Feb-2023 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10
implement mode2 reset on smu_v13_0_10
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-
drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10
implement mode2 reset on smu_v13_0_10
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60 |
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#
0ad7347a |
| 10-Aug-2022 |
André Almeida <andrealmeid@igalia.com> |
drm/amd: Add detailed GFXOFF stats to debugfs
Add debugfs interface to log GFXOFF statistics:
- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the time of query since system powe
drm/amd: Add detailed GFXOFF stats to debugfs
Add debugfs interface to log GFXOFF statistics:
- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the time of query since system power-up
- Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to get average GFXOFF residency % multiplied by 100 during the last logging interval.
Both features are designed to be keep the values persistent between suspends.
Signed-off-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55 |
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#
50fe04d4 |
| 14-Jul-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: introduce runtime pm mode
It can benefit code consistency in future.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Laz
drm/amdgpu: introduce runtime pm mode
It can benefit code consistency in future.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18 |
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#
7101ab97 |
| 18-May-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function
GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Hua
drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function
GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27 |
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#
d510eccf |
| 03-Mar-2022 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amd/pm: add send bad channel info function
support message SMU update bad channel info to update HBM bad channel info in OOB table
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by
drm/amd/pm: add send bad channel info function
support message SMU update bad channel info to update HBM bad channel info in OOB table
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16 |
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#
b874c667 |
| 18-Jan-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: correct the default DriverSmuConfig table settings
For Some ASICs, with the PMFW default settings, we may see the power consumption reported via metrics table is "Very Erratic". With the
drm/amd/pm: correct the default DriverSmuConfig table settings
For Some ASICs, with the PMFW default settings, we may see the power consumption reported via metrics table is "Very Erratic". With the socket power alpha filter set as 10/100ms, we can correct that issue.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f54b6bdf |
| 02-Feb-2022 |
Maíra Canal <maira.canal@usp.br> |
drm/amd/pm: add missing prototypes to amdgpu_dpm_internal
Include the header with the prototype to silence the following clang warnings:
drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:29:6:
drm/amd/pm: add missing prototypes to amdgpu_dpm_internal
Include the header with the prototype to silence the following clang warnings:
drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:29:6: warning: no previous prototype for function 'amdgpu_dpm_get_active_displays' [-Wmissing-prototypes] void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:29:1: note: declare 'static' if the function is not intended to be used outside of this translation unit void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) ^ static drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:76:5: warning: no previous prototype for function 'amdgpu_dpm_get_vrefresh' [-Wmissing-prototypes] u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:76:1: note: declare 'static' if the function is not intended to be used outside of this translation unit u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) ^ static 2 warnings generated.
Besides that, remove the duplicated prototype of the function amdgpu_dpm_get_vblank_time in order to keep the consistency of the headers.
Fixes: 6ddbd37f1074 ("drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementations") Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Maíra Canal <maira.canal@usp.br> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7 |
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#
5d64f9bb |
| 03-Dec-2021 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset
(v3) Rewrote patchset to order patches as (API, hw impl, usecase)
- added API for new power manag
amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset
(v3) Rewrote patchset to order patches as (API, hw impl, usecase)
- added API for new power management function emit_clk_levels This function should duplicate the functionality of print_clk_levels, but this solution passes the buffer base and write offset down the stack. - new powerplay function emit_clock_levels, implemented by smu_emit_ppclk_levels() This function parallels the implementation of smu_print_ppclk_levels and calls emit_clk_levels, and allows the returns of errors - new helper function smu_convert_to_smuclk called by smu_print_ppclk_levels and smu_emit_ppclk_levels
Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-By: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8cda7a4f |
| 07-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates
Add a new CTX ioctl operation to set stable pstates for profiling. When creating traces for tools like RGP or using SPM or doing performance
drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates
Add a new CTX ioctl operation to set stable pstates for profiling. When creating traces for tools like RGP or using SPM or doing performance profiling, it's required to enable a special stable profiling power state on the GPU. These profiling states set fixed clocks and disable certain other power features like powergating which may impact the results.
Historically, these profiling pstates were enabled via sysfs, but this adds an interface to enable it via the CTX ioctl from the application. Since the power state is global only one application can set it at a time, so if multiple applications try and use it only the first will get it, the ioctl will return -EBUSY for others. The sysfs interface will override whatever has been set by this interface.
Mesa MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/207
v2: don't default r = 0; v3: rebase on Evan's PM cleanup
Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f60dd50 |
| 19-Jan-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amd: Expose the FRU SMU I2C bus
Expose both SMU I2C buses. Some boards use the same bus for both the RAS and FRU EEPROMs and others use different buses. This enables the additional I2C bus and
drm/amd: Expose the FRU SMU I2C bus
Expose both SMU I2C buses. Some boards use the same bus for both the RAS and FRU EEPROMs and others use different buses. This enables the additional I2C bus and sets the right buses to use for RAS and FRU EEPROM access.
Cc: Roy Sun <Roy.Sun@amd.com> Co-developed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2 |
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#
7689dab4 |
| 10-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop redundant or unused APIs and data structures
Drop those unused APIs and data structures.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> S
drm/amd/pm: drop redundant or unused APIs and data structures
Drop those unused APIs and data structures.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ddbd37f |
| 16-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementations
Drop cross callings and multi-function APIs. Also avoid exposing internal implementations details.
Signed-off-by: Evan Quan <evan
drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementations
Drop cross callings and multi-function APIs. Also avoid exposing internal implementations details.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d698a2c4 |
| 15-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: move pp_force_state_enabled member to amdgpu_pm structure
As it lables an internal pm state and amdgpu_pm structure is the more proper place than amdgpu_device structure for it.
Signed-
drm/amd/pm: move pp_force_state_enabled member to amdgpu_pm structure
As it lables an internal pm state and amdgpu_pm structure is the more proper place than amdgpu_device structure for it.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
84176663 |
| 11-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)
Those APIs are used only by legacy ASICs(si/kv). They cannot be shared by other ASICs. So, we create a new holder for
drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)
Those APIs are used only by legacy ASICs(si/kv). They cannot be shared by other ASICs. So, we create a new holder for them.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
28a31774 |
| 11-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose the API used internally only in kv_dpm.c
Move it to kv_dpm.c instead.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-
drm/amd/pm: do not expose the API used internally only in kv_dpm.c
Move it to kv_dpm.c instead.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a79110f2 |
| 10-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose those APIs used internally only in si_dpm.c
Move them to si_dpm.c instead.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed
drm/amd/pm: do not expose those APIs used internally only in si_dpm.c
Move them to si_dpm.c instead.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d4481576 |
| 10-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose those APIs used internally only in amdgpu_dpm.c
Move them to amdgpu_dpm.c instead.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com
drm/amd/pm: do not expose those APIs used internally only in amdgpu_dpm.c
Move them to amdgpu_dpm.c instead.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
13f5dbd6 |
| 21-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose power implementation details to display
Display is another client of our power APIs. It's not proper to spike into power implementation details there.
Signed-off-by: Evan
drm/amd/pm: do not expose power implementation details to display
Display is another client of our power APIs. It's not proper to spike into power implementation details there.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
79c65f3f |
| 21-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose power implementation details to amdgpu_pm.c
amdgpu_pm.c holds all the user sysfs/hwmon interfaces. It's another client of our power APIs. It's not proper to spike into powe
drm/amd/pm: do not expose power implementation details to amdgpu_pm.c
amdgpu_pm.c holds all the user sysfs/hwmon interfaces. It's another client of our power APIs. It's not proper to spike into power implementation details there.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bc143d8b |
| 21-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose implementation details to other blocks out of power
Those implementation details(whether swsmu supported, some ppt_funcs supported, accessing internal statistics ...)should
drm/amd/pm: do not expose implementation details to other blocks out of power
Those implementation details(whether swsmu supported, some ppt_funcs supported, accessing internal statistics ...)should be kept internally. It's not a good practice and even error prone to expose implementation details.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7e31a858 |
| 12-Dec-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: move smu_debug_mask to a more proper place
As the smu_context will be invisible from outside(of power). Also, the smu_debug_mask can be shared around all power code instead of some speci
drm/amdgpu: move smu_debug_mask to a more proper place
As the smu_context will be invisible from outside(of power). Also, the smu_debug_mask can be shared around all power code instead of some specific framework(swSMU) only.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.1 |
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#
6c08e0ef |
| 05-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: avoid duplicate powergate/ungate setting
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may
drm/amd/pm: avoid duplicate powergate/ungate setting
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may cause unexpected issues.
Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/ Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789 Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Borislav Petkov <bp@suse.de> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ee27ee2 |
| 05-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: avoid duplicate powergate/ungate setting
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may
drm/amd/pm: avoid duplicate powergate/ungate setting
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may cause unexpected issues.
Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/ Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789 Fixes: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend") Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Borislav Petkov <bp@suse.de> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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