1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 /* Argument for PPSMC_MSG_GpuChangeState */ 27 enum gfx_change_state { 28 sGpuChangeState_D0Entry = 1, 29 sGpuChangeState_D3Entry, 30 }; 31 32 enum amdgpu_int_thermal_type { 33 THERMAL_TYPE_NONE, 34 THERMAL_TYPE_EXTERNAL, 35 THERMAL_TYPE_EXTERNAL_GPIO, 36 THERMAL_TYPE_RV6XX, 37 THERMAL_TYPE_RV770, 38 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 39 THERMAL_TYPE_EVERGREEN, 40 THERMAL_TYPE_SUMO, 41 THERMAL_TYPE_NI, 42 THERMAL_TYPE_SI, 43 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 44 THERMAL_TYPE_CI, 45 THERMAL_TYPE_KV, 46 }; 47 48 enum amdgpu_dpm_auto_throttle_src { 49 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 50 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 51 }; 52 53 enum amdgpu_dpm_event_src { 54 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 55 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 56 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 57 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 58 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 59 }; 60 61 struct amdgpu_ps { 62 u32 caps; /* vbios flags */ 63 u32 class; /* vbios flags */ 64 u32 class2; /* vbios flags */ 65 /* UVD clocks */ 66 u32 vclk; 67 u32 dclk; 68 /* VCE clocks */ 69 u32 evclk; 70 u32 ecclk; 71 bool vce_active; 72 enum amd_vce_level vce_level; 73 /* asic priv */ 74 void *ps_priv; 75 }; 76 77 struct amdgpu_dpm_thermal { 78 /* thermal interrupt work */ 79 struct work_struct work; 80 /* low temperature threshold */ 81 int min_temp; 82 /* high temperature threshold */ 83 int max_temp; 84 /* edge max emergency(shutdown) temp */ 85 int max_edge_emergency_temp; 86 /* hotspot low temperature threshold */ 87 int min_hotspot_temp; 88 /* hotspot high temperature critical threshold */ 89 int max_hotspot_crit_temp; 90 /* hotspot max emergency(shutdown) temp */ 91 int max_hotspot_emergency_temp; 92 /* memory low temperature threshold */ 93 int min_mem_temp; 94 /* memory high temperature critical threshold */ 95 int max_mem_crit_temp; 96 /* memory max emergency(shutdown) temp */ 97 int max_mem_emergency_temp; 98 /* was last interrupt low to high or high to low */ 99 bool high_to_low; 100 /* interrupt source */ 101 struct amdgpu_irq_src irq; 102 }; 103 104 enum amdgpu_clk_action 105 { 106 AMDGPU_SCLK_UP = 1, 107 AMDGPU_SCLK_DOWN 108 }; 109 110 struct amdgpu_blacklist_clocks 111 { 112 u32 sclk; 113 u32 mclk; 114 enum amdgpu_clk_action action; 115 }; 116 117 struct amdgpu_clock_and_voltage_limits { 118 u32 sclk; 119 u32 mclk; 120 u16 vddc; 121 u16 vddci; 122 }; 123 124 struct amdgpu_clock_array { 125 u32 count; 126 u32 *values; 127 }; 128 129 struct amdgpu_clock_voltage_dependency_entry { 130 u32 clk; 131 u16 v; 132 }; 133 134 struct amdgpu_clock_voltage_dependency_table { 135 u32 count; 136 struct amdgpu_clock_voltage_dependency_entry *entries; 137 }; 138 139 union amdgpu_cac_leakage_entry { 140 struct { 141 u16 vddc; 142 u32 leakage; 143 }; 144 struct { 145 u16 vddc1; 146 u16 vddc2; 147 u16 vddc3; 148 }; 149 }; 150 151 struct amdgpu_cac_leakage_table { 152 u32 count; 153 union amdgpu_cac_leakage_entry *entries; 154 }; 155 156 struct amdgpu_phase_shedding_limits_entry { 157 u16 voltage; 158 u32 sclk; 159 u32 mclk; 160 }; 161 162 struct amdgpu_phase_shedding_limits_table { 163 u32 count; 164 struct amdgpu_phase_shedding_limits_entry *entries; 165 }; 166 167 struct amdgpu_uvd_clock_voltage_dependency_entry { 168 u32 vclk; 169 u32 dclk; 170 u16 v; 171 }; 172 173 struct amdgpu_uvd_clock_voltage_dependency_table { 174 u8 count; 175 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 176 }; 177 178 struct amdgpu_vce_clock_voltage_dependency_entry { 179 u32 ecclk; 180 u32 evclk; 181 u16 v; 182 }; 183 184 struct amdgpu_vce_clock_voltage_dependency_table { 185 u8 count; 186 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 187 }; 188 189 struct amdgpu_ppm_table { 190 u8 ppm_design; 191 u16 cpu_core_number; 192 u32 platform_tdp; 193 u32 small_ac_platform_tdp; 194 u32 platform_tdc; 195 u32 small_ac_platform_tdc; 196 u32 apu_tdp; 197 u32 dgpu_tdp; 198 u32 dgpu_ulv_power; 199 u32 tj_max; 200 }; 201 202 struct amdgpu_cac_tdp_table { 203 u16 tdp; 204 u16 configurable_tdp; 205 u16 tdc; 206 u16 battery_power_limit; 207 u16 small_power_limit; 208 u16 low_cac_leakage; 209 u16 high_cac_leakage; 210 u16 maximum_power_delivery_limit; 211 }; 212 213 struct amdgpu_dpm_dynamic_state { 214 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 215 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 216 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 217 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 218 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 219 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 220 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 221 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 222 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 223 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 224 struct amdgpu_clock_array valid_sclk_values; 225 struct amdgpu_clock_array valid_mclk_values; 226 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 227 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 228 u32 mclk_sclk_ratio; 229 u32 sclk_mclk_delta; 230 u16 vddc_vddci_delta; 231 u16 min_vddc_for_pcie_gen2; 232 struct amdgpu_cac_leakage_table cac_leakage_table; 233 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 234 struct amdgpu_ppm_table *ppm_table; 235 struct amdgpu_cac_tdp_table *cac_tdp_table; 236 }; 237 238 struct amdgpu_dpm_fan { 239 u16 t_min; 240 u16 t_med; 241 u16 t_high; 242 u16 pwm_min; 243 u16 pwm_med; 244 u16 pwm_high; 245 u8 t_hyst; 246 u32 cycle_delay; 247 u16 t_max; 248 u8 control_mode; 249 u16 default_max_fan_pwm; 250 u16 default_fan_output_sensitivity; 251 u16 fan_output_sensitivity; 252 bool ucode_fan_control; 253 }; 254 255 enum amdgpu_pcie_gen { 256 AMDGPU_PCIE_GEN1 = 0, 257 AMDGPU_PCIE_GEN2 = 1, 258 AMDGPU_PCIE_GEN3 = 2, 259 AMDGPU_PCIE_GEN_INVALID = 0xffff 260 }; 261 262 #define amdgpu_dpm_reset_power_profile_state(adev, request) \ 263 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ 264 (adev)->powerplay.pp_handle, request)) 265 266 struct amdgpu_dpm { 267 struct amdgpu_ps *ps; 268 /* number of valid power states */ 269 int num_ps; 270 /* current power state that is active */ 271 struct amdgpu_ps *current_ps; 272 /* requested power state */ 273 struct amdgpu_ps *requested_ps; 274 /* boot up power state */ 275 struct amdgpu_ps *boot_ps; 276 /* default uvd power state */ 277 struct amdgpu_ps *uvd_ps; 278 /* vce requirements */ 279 u32 num_of_vce_states; 280 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 281 enum amd_vce_level vce_level; 282 enum amd_pm_state_type state; 283 enum amd_pm_state_type user_state; 284 enum amd_pm_state_type last_state; 285 enum amd_pm_state_type last_user_state; 286 u32 platform_caps; 287 u32 voltage_response_time; 288 u32 backbias_response_time; 289 void *priv; 290 u32 new_active_crtcs; 291 int new_active_crtc_count; 292 u32 current_active_crtcs; 293 int current_active_crtc_count; 294 struct amdgpu_dpm_dynamic_state dyn_state; 295 struct amdgpu_dpm_fan fan; 296 u32 tdp_limit; 297 u32 near_tdp_limit; 298 u32 near_tdp_limit_adjusted; 299 u32 sq_ramping_threshold; 300 u32 cac_leakage; 301 u16 tdp_od_limit; 302 u32 tdp_adjustment; 303 u16 load_line_slope; 304 bool power_control; 305 /* special states active */ 306 bool thermal_active; 307 bool uvd_active; 308 bool vce_active; 309 /* thermal handling */ 310 struct amdgpu_dpm_thermal thermal; 311 /* forced levels */ 312 enum amd_dpm_forced_level forced_level; 313 }; 314 315 enum ip_power_state { 316 POWER_STATE_UNKNOWN, 317 POWER_STATE_ON, 318 POWER_STATE_OFF, 319 }; 320 321 /* Used to mask smu debug modes */ 322 #define SMU_DEBUG_HALT_ON_ERROR 0x1 323 324 struct amdgpu_pm { 325 struct mutex mutex; 326 u32 current_sclk; 327 u32 current_mclk; 328 u32 default_sclk; 329 u32 default_mclk; 330 struct amdgpu_i2c_chan *i2c_bus; 331 bool bus_locked; 332 /* internal thermal controller on rv6xx+ */ 333 enum amdgpu_int_thermal_type int_thermal_type; 334 struct device *int_hwmon_dev; 335 /* fan control parameters */ 336 bool no_fan; 337 u8 fan_pulses_per_revolution; 338 u8 fan_min_rpm; 339 u8 fan_max_rpm; 340 /* dpm */ 341 bool dpm_enabled; 342 bool sysfs_initialized; 343 struct amdgpu_dpm dpm; 344 const struct firmware *fw; /* SMC firmware */ 345 uint32_t fw_version; 346 uint32_t pcie_gen_mask; 347 uint32_t pcie_mlw_mask; 348 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 349 uint32_t smu_prv_buffer_size; 350 struct amdgpu_bo *smu_prv_buffer; 351 bool ac_power; 352 /* powerplay feature */ 353 uint32_t pp_feature; 354 355 /* Used for I2C access to various EEPROMs on relevant ASICs */ 356 struct i2c_adapter smu_i2c; 357 struct mutex smu_i2c_mutex; 358 struct list_head pm_attr_list; 359 360 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; 361 362 /* 363 * 0 = disabled (default), otherwise enable corresponding debug mode 364 */ 365 uint32_t smu_debug_mask; 366 }; 367 368 #define R600_SSTU_DFLT 0 369 #define R600_SST_DFLT 0x00C8 370 371 /* XXX are these ok? */ 372 #define R600_TEMP_RANGE_MIN (90 * 1000) 373 #define R600_TEMP_RANGE_MAX (120 * 1000) 374 375 #define FDO_PWM_MODE_STATIC 1 376 #define FDO_PWM_MODE_STATIC_RPM 5 377 378 enum amdgpu_td { 379 AMDGPU_TD_AUTO, 380 AMDGPU_TD_UP, 381 AMDGPU_TD_DOWN, 382 }; 383 384 enum amdgpu_display_watermark { 385 AMDGPU_DISPLAY_WATERMARK_LOW = 0, 386 AMDGPU_DISPLAY_WATERMARK_HIGH = 1, 387 }; 388 389 enum amdgpu_display_gap 390 { 391 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 392 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, 393 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, 394 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, 395 }; 396 397 void amdgpu_dpm_print_class_info(u32 class, u32 class2); 398 void amdgpu_dpm_print_cap_info(u32 caps); 399 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 400 struct amdgpu_ps *rps); 401 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 402 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 403 void *data, uint32_t *size); 404 405 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); 406 407 int amdgpu_get_platform_caps(struct amdgpu_device *adev); 408 409 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 410 void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 411 412 void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 413 414 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, 415 u32 sys_mask, 416 enum amdgpu_pcie_gen asic_gen, 417 enum amdgpu_pcie_gen default_gen); 418 419 struct amd_vce_state* 420 amdgpu_get_vce_clock_state(void *handle, u32 idx); 421 422 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 423 uint32_t block_type, bool gate); 424 425 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 426 427 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 428 429 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 430 uint32_t pstate); 431 432 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 433 enum PP_SMC_POWER_PROFILE type, 434 bool en); 435 436 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); 437 438 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); 439 440 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); 441 442 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); 443 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); 444 445 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 446 enum pp_mp1_state mp1_state); 447 448 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); 449 450 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); 451 452 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 453 uint32_t cstate); 454 455 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en); 456 457 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); 458 459 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 460 uint32_t msg_id); 461 462 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 463 bool acquire); 464 465 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 466 467 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 468 void *data, uint32_t *size); 469 470 void amdgpu_dpm_thermal_work_handler(struct work_struct *work); 471 472 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev); 473 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); 474 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); 475 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); 476 void amdgpu_pm_print_power_states(struct amdgpu_device *adev); 477 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); 478 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); 479 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); 480 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 481 enum pp_clock_type type, 482 uint32_t *min, 483 uint32_t *max); 484 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 485 enum pp_clock_type type, 486 uint32_t min, 487 uint32_t max); 488 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); 489 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 490 uint64_t event_arg); 491 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 492 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); 493 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 494 enum gfx_change_state state); 495 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 496 void *umc_ecc); 497 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 498 uint32_t idx); 499 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state); 500 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 501 enum amd_pm_state_type state); 502 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev); 503 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 504 enum amd_dpm_forced_level level); 505 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 506 struct pp_states_info *states); 507 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 508 enum amd_pp_task task_id, 509 enum amd_pm_state_type *user_state); 510 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table); 511 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 512 uint32_t type, 513 long *input, 514 uint32_t size); 515 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 516 uint32_t type, 517 long *input, 518 uint32_t size); 519 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 520 enum pp_clock_type type, 521 char *buf); 522 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 523 uint64_t ppfeature_masks); 524 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf); 525 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 526 enum pp_clock_type type, 527 uint32_t mask); 528 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev); 529 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value); 530 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev); 531 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value); 532 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 533 char *buf); 534 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 535 long *input, uint32_t size); 536 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); 537 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 538 uint32_t *fan_mode); 539 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 540 uint32_t speed); 541 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 542 uint32_t *speed); 543 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 544 uint32_t *speed); 545 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 546 uint32_t speed); 547 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 548 uint32_t mode); 549 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 550 uint32_t *limit, 551 enum pp_power_limit_level pp_limit_level, 552 enum pp_power_type power_type); 553 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 554 uint32_t limit); 555 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); 556 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 557 struct seq_file *m); 558 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 559 void **addr, 560 size_t *size); 561 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); 562 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 563 const char *buf, 564 size_t size); 565 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev); 566 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev); 567 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 568 const struct amd_pp_display_configuration *input); 569 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 570 enum amd_pp_clock_type type, 571 struct amd_pp_clocks *clocks); 572 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 573 struct amd_pp_simple_clock_info *clocks); 574 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 575 enum amd_pp_clock_type type, 576 struct pp_clock_levels_with_latency *clocks); 577 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 578 enum amd_pp_clock_type type, 579 struct pp_clock_levels_with_voltage *clocks); 580 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 581 void *clock_ranges); 582 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 583 struct pp_display_clock_request *clock); 584 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 585 struct amd_pp_clock_info *clocks); 586 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev); 587 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 588 uint32_t count); 589 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 590 uint32_t clock); 591 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 592 uint32_t clock); 593 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 594 uint32_t clock); 595 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 596 bool disable_memory_clock_switch); 597 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 598 struct pp_smu_nv_clock_table *max_clocks); 599 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 600 unsigned int *clock_values_in_khz, 601 unsigned int *num_states); 602 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 603 struct dpm_clocks *clock_table); 604 #endif 605