1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 /* Argument for PPSMC_MSG_GpuChangeState */ 27 enum gfx_change_state { 28 sGpuChangeState_D0Entry = 1, 29 sGpuChangeState_D3Entry, 30 }; 31 32 enum amdgpu_int_thermal_type { 33 THERMAL_TYPE_NONE, 34 THERMAL_TYPE_EXTERNAL, 35 THERMAL_TYPE_EXTERNAL_GPIO, 36 THERMAL_TYPE_RV6XX, 37 THERMAL_TYPE_RV770, 38 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 39 THERMAL_TYPE_EVERGREEN, 40 THERMAL_TYPE_SUMO, 41 THERMAL_TYPE_NI, 42 THERMAL_TYPE_SI, 43 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 44 THERMAL_TYPE_CI, 45 THERMAL_TYPE_KV, 46 }; 47 48 struct amdgpu_ps { 49 u32 caps; /* vbios flags */ 50 u32 class; /* vbios flags */ 51 u32 class2; /* vbios flags */ 52 /* UVD clocks */ 53 u32 vclk; 54 u32 dclk; 55 /* VCE clocks */ 56 u32 evclk; 57 u32 ecclk; 58 bool vce_active; 59 enum amd_vce_level vce_level; 60 /* asic priv */ 61 void *ps_priv; 62 }; 63 64 struct amdgpu_dpm_thermal { 65 /* thermal interrupt work */ 66 struct work_struct work; 67 /* low temperature threshold */ 68 int min_temp; 69 /* high temperature threshold */ 70 int max_temp; 71 /* edge max emergency(shutdown) temp */ 72 int max_edge_emergency_temp; 73 /* hotspot low temperature threshold */ 74 int min_hotspot_temp; 75 /* hotspot high temperature critical threshold */ 76 int max_hotspot_crit_temp; 77 /* hotspot max emergency(shutdown) temp */ 78 int max_hotspot_emergency_temp; 79 /* memory low temperature threshold */ 80 int min_mem_temp; 81 /* memory high temperature critical threshold */ 82 int max_mem_crit_temp; 83 /* memory max emergency(shutdown) temp */ 84 int max_mem_emergency_temp; 85 /* was last interrupt low to high or high to low */ 86 bool high_to_low; 87 /* interrupt source */ 88 struct amdgpu_irq_src irq; 89 }; 90 91 enum amdgpu_clk_action 92 { 93 AMDGPU_SCLK_UP = 1, 94 AMDGPU_SCLK_DOWN 95 }; 96 97 struct amdgpu_blacklist_clocks 98 { 99 u32 sclk; 100 u32 mclk; 101 enum amdgpu_clk_action action; 102 }; 103 104 struct amdgpu_clock_and_voltage_limits { 105 u32 sclk; 106 u32 mclk; 107 u16 vddc; 108 u16 vddci; 109 }; 110 111 struct amdgpu_clock_array { 112 u32 count; 113 u32 *values; 114 }; 115 116 struct amdgpu_clock_voltage_dependency_entry { 117 u32 clk; 118 u16 v; 119 }; 120 121 struct amdgpu_clock_voltage_dependency_table { 122 u32 count; 123 struct amdgpu_clock_voltage_dependency_entry *entries; 124 }; 125 126 union amdgpu_cac_leakage_entry { 127 struct { 128 u16 vddc; 129 u32 leakage; 130 }; 131 struct { 132 u16 vddc1; 133 u16 vddc2; 134 u16 vddc3; 135 }; 136 }; 137 138 struct amdgpu_cac_leakage_table { 139 u32 count; 140 union amdgpu_cac_leakage_entry *entries; 141 }; 142 143 struct amdgpu_phase_shedding_limits_entry { 144 u16 voltage; 145 u32 sclk; 146 u32 mclk; 147 }; 148 149 struct amdgpu_phase_shedding_limits_table { 150 u32 count; 151 struct amdgpu_phase_shedding_limits_entry *entries; 152 }; 153 154 struct amdgpu_uvd_clock_voltage_dependency_entry { 155 u32 vclk; 156 u32 dclk; 157 u16 v; 158 }; 159 160 struct amdgpu_uvd_clock_voltage_dependency_table { 161 u8 count; 162 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 163 }; 164 165 struct amdgpu_vce_clock_voltage_dependency_entry { 166 u32 ecclk; 167 u32 evclk; 168 u16 v; 169 }; 170 171 struct amdgpu_vce_clock_voltage_dependency_table { 172 u8 count; 173 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 174 }; 175 176 struct amdgpu_ppm_table { 177 u8 ppm_design; 178 u16 cpu_core_number; 179 u32 platform_tdp; 180 u32 small_ac_platform_tdp; 181 u32 platform_tdc; 182 u32 small_ac_platform_tdc; 183 u32 apu_tdp; 184 u32 dgpu_tdp; 185 u32 dgpu_ulv_power; 186 u32 tj_max; 187 }; 188 189 struct amdgpu_cac_tdp_table { 190 u16 tdp; 191 u16 configurable_tdp; 192 u16 tdc; 193 u16 battery_power_limit; 194 u16 small_power_limit; 195 u16 low_cac_leakage; 196 u16 high_cac_leakage; 197 u16 maximum_power_delivery_limit; 198 }; 199 200 struct amdgpu_dpm_dynamic_state { 201 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 202 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 203 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 204 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 205 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 206 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 207 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 208 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 209 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 210 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 211 struct amdgpu_clock_array valid_sclk_values; 212 struct amdgpu_clock_array valid_mclk_values; 213 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 214 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 215 u32 mclk_sclk_ratio; 216 u32 sclk_mclk_delta; 217 u16 vddc_vddci_delta; 218 u16 min_vddc_for_pcie_gen2; 219 struct amdgpu_cac_leakage_table cac_leakage_table; 220 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 221 struct amdgpu_ppm_table *ppm_table; 222 struct amdgpu_cac_tdp_table *cac_tdp_table; 223 }; 224 225 struct amdgpu_dpm_fan { 226 u16 t_min; 227 u16 t_med; 228 u16 t_high; 229 u16 pwm_min; 230 u16 pwm_med; 231 u16 pwm_high; 232 u8 t_hyst; 233 u32 cycle_delay; 234 u16 t_max; 235 u8 control_mode; 236 u16 default_max_fan_pwm; 237 u16 default_fan_output_sensitivity; 238 u16 fan_output_sensitivity; 239 bool ucode_fan_control; 240 }; 241 242 #define amdgpu_dpm_reset_power_profile_state(adev, request) \ 243 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ 244 (adev)->powerplay.pp_handle, request)) 245 246 struct amdgpu_dpm { 247 struct amdgpu_ps *ps; 248 /* number of valid power states */ 249 int num_ps; 250 /* current power state that is active */ 251 struct amdgpu_ps *current_ps; 252 /* requested power state */ 253 struct amdgpu_ps *requested_ps; 254 /* boot up power state */ 255 struct amdgpu_ps *boot_ps; 256 /* default uvd power state */ 257 struct amdgpu_ps *uvd_ps; 258 /* vce requirements */ 259 u32 num_of_vce_states; 260 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 261 enum amd_vce_level vce_level; 262 enum amd_pm_state_type state; 263 enum amd_pm_state_type user_state; 264 enum amd_pm_state_type last_state; 265 enum amd_pm_state_type last_user_state; 266 u32 platform_caps; 267 u32 voltage_response_time; 268 u32 backbias_response_time; 269 void *priv; 270 u32 new_active_crtcs; 271 int new_active_crtc_count; 272 u32 current_active_crtcs; 273 int current_active_crtc_count; 274 struct amdgpu_dpm_dynamic_state dyn_state; 275 struct amdgpu_dpm_fan fan; 276 u32 tdp_limit; 277 u32 near_tdp_limit; 278 u32 near_tdp_limit_adjusted; 279 u32 sq_ramping_threshold; 280 u32 cac_leakage; 281 u16 tdp_od_limit; 282 u32 tdp_adjustment; 283 u16 load_line_slope; 284 bool power_control; 285 /* special states active */ 286 bool thermal_active; 287 bool uvd_active; 288 bool vce_active; 289 /* thermal handling */ 290 struct amdgpu_dpm_thermal thermal; 291 /* forced levels */ 292 enum amd_dpm_forced_level forced_level; 293 }; 294 295 enum ip_power_state { 296 POWER_STATE_UNKNOWN, 297 POWER_STATE_ON, 298 POWER_STATE_OFF, 299 }; 300 301 /* Used to mask smu debug modes */ 302 #define SMU_DEBUG_HALT_ON_ERROR 0x1 303 304 struct amdgpu_pm { 305 struct mutex mutex; 306 u32 current_sclk; 307 u32 current_mclk; 308 u32 default_sclk; 309 u32 default_mclk; 310 struct amdgpu_i2c_chan *i2c_bus; 311 bool bus_locked; 312 /* internal thermal controller on rv6xx+ */ 313 enum amdgpu_int_thermal_type int_thermal_type; 314 struct device *int_hwmon_dev; 315 /* fan control parameters */ 316 bool no_fan; 317 u8 fan_pulses_per_revolution; 318 u8 fan_min_rpm; 319 u8 fan_max_rpm; 320 /* dpm */ 321 bool dpm_enabled; 322 bool sysfs_initialized; 323 struct amdgpu_dpm dpm; 324 const struct firmware *fw; /* SMC firmware */ 325 uint32_t fw_version; 326 uint32_t pcie_gen_mask; 327 uint32_t pcie_mlw_mask; 328 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 329 uint32_t smu_prv_buffer_size; 330 struct amdgpu_bo *smu_prv_buffer; 331 bool ac_power; 332 /* powerplay feature */ 333 uint32_t pp_feature; 334 335 /* Used for I2C access to various EEPROMs on relevant ASICs */ 336 struct i2c_adapter smu_i2c; 337 struct mutex smu_i2c_mutex; 338 struct list_head pm_attr_list; 339 340 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; 341 342 /* 343 * 0 = disabled (default), otherwise enable corresponding debug mode 344 */ 345 uint32_t smu_debug_mask; 346 }; 347 348 #define R600_SSTU_DFLT 0 349 #define R600_SST_DFLT 0x00C8 350 351 /* XXX are these ok? */ 352 #define R600_TEMP_RANGE_MIN (90 * 1000) 353 #define R600_TEMP_RANGE_MAX (120 * 1000) 354 355 #define FDO_PWM_MODE_STATIC 1 356 #define FDO_PWM_MODE_STATIC_RPM 5 357 358 enum amdgpu_td { 359 AMDGPU_TD_AUTO, 360 AMDGPU_TD_UP, 361 AMDGPU_TD_DOWN, 362 }; 363 364 enum amdgpu_display_watermark { 365 AMDGPU_DISPLAY_WATERMARK_LOW = 0, 366 AMDGPU_DISPLAY_WATERMARK_HIGH = 1, 367 }; 368 369 enum amdgpu_display_gap 370 { 371 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 372 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, 373 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, 374 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, 375 }; 376 377 void amdgpu_dpm_print_class_info(u32 class, u32 class2); 378 void amdgpu_dpm_print_cap_info(u32 caps); 379 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 380 struct amdgpu_ps *rps); 381 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 382 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 383 void *data, uint32_t *size); 384 385 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); 386 387 int amdgpu_get_platform_caps(struct amdgpu_device *adev); 388 389 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 390 void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 391 392 void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 393 394 struct amd_vce_state* 395 amdgpu_get_vce_clock_state(void *handle, u32 idx); 396 397 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 398 uint32_t block_type, bool gate); 399 400 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 401 402 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 403 404 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 405 uint32_t pstate); 406 407 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 408 enum PP_SMC_POWER_PROFILE type, 409 bool en); 410 411 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); 412 413 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); 414 415 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); 416 417 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); 418 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); 419 420 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 421 enum pp_mp1_state mp1_state); 422 423 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); 424 425 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); 426 427 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 428 uint32_t cstate); 429 430 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en); 431 432 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); 433 434 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 435 uint32_t msg_id); 436 437 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 438 bool acquire); 439 440 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 441 442 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 443 void *data, uint32_t *size); 444 445 void amdgpu_dpm_thermal_work_handler(struct work_struct *work); 446 447 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev); 448 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); 449 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); 450 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); 451 void amdgpu_pm_print_power_states(struct amdgpu_device *adev); 452 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); 453 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); 454 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); 455 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 456 enum pp_clock_type type, 457 uint32_t *min, 458 uint32_t *max); 459 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 460 enum pp_clock_type type, 461 uint32_t min, 462 uint32_t max); 463 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); 464 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 465 uint64_t event_arg); 466 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 467 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); 468 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 469 enum gfx_change_state state); 470 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 471 void *umc_ecc); 472 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 473 uint32_t idx); 474 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state); 475 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 476 enum amd_pm_state_type state); 477 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev); 478 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 479 enum amd_dpm_forced_level level); 480 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 481 struct pp_states_info *states); 482 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 483 enum amd_pp_task task_id, 484 enum amd_pm_state_type *user_state); 485 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table); 486 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 487 uint32_t type, 488 long *input, 489 uint32_t size); 490 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 491 uint32_t type, 492 long *input, 493 uint32_t size); 494 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 495 enum pp_clock_type type, 496 char *buf); 497 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 498 uint64_t ppfeature_masks); 499 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf); 500 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 501 enum pp_clock_type type, 502 uint32_t mask); 503 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev); 504 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value); 505 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev); 506 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value); 507 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 508 char *buf); 509 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 510 long *input, uint32_t size); 511 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); 512 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 513 uint32_t *fan_mode); 514 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 515 uint32_t speed); 516 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 517 uint32_t *speed); 518 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 519 uint32_t *speed); 520 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 521 uint32_t speed); 522 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 523 uint32_t mode); 524 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 525 uint32_t *limit, 526 enum pp_power_limit_level pp_limit_level, 527 enum pp_power_type power_type); 528 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 529 uint32_t limit); 530 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); 531 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 532 struct seq_file *m); 533 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 534 void **addr, 535 size_t *size); 536 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); 537 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 538 const char *buf, 539 size_t size); 540 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev); 541 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev); 542 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 543 const struct amd_pp_display_configuration *input); 544 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 545 enum amd_pp_clock_type type, 546 struct amd_pp_clocks *clocks); 547 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 548 struct amd_pp_simple_clock_info *clocks); 549 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 550 enum amd_pp_clock_type type, 551 struct pp_clock_levels_with_latency *clocks); 552 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 553 enum amd_pp_clock_type type, 554 struct pp_clock_levels_with_voltage *clocks); 555 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 556 void *clock_ranges); 557 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 558 struct pp_display_clock_request *clock); 559 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 560 struct amd_pp_clock_info *clocks); 561 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev); 562 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 563 uint32_t count); 564 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 565 uint32_t clock); 566 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 567 uint32_t clock); 568 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 569 uint32_t clock); 570 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 571 bool disable_memory_clock_switch); 572 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 573 struct pp_smu_nv_clock_table *max_clocks); 574 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 575 unsigned int *clock_values_in_khz, 576 unsigned int *num_states); 577 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 578 struct dpm_clocks *clock_table); 579 #endif 580