Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32 |
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#
1598fc57 |
| 01-Jun-2023 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Program OTG vtotal min/max selectors unconditionally for DCN1+
For FPO/FAMS, DMCUB will try to change the output timings by writing to the OTG registers. However, the timings writte
drm/amd/display: Program OTG vtotal min/max selectors unconditionally for DCN1+
For FPO/FAMS, DMCUB will try to change the output timings by writing to the OTG registers. However, the timings written directly to the OTG registers will not be honoured unless VMIN/VMAX selector registers are programmed with the right bits and trigger source is selected correctly. Proper solution needs to go into DMCUB but will require additional state tracking to ensure that the selectors are set and reset correctly as per driver state. Until fix is merged into firmware, apply the workaround in driver to unconditionally write OTG vmin/vmax selectors.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a4d4db72 |
| 02-Jun-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/display: Fix dc/dcn20/dcn20_optc.c kdoc
Fix all kdoc warnings in dc/dcn20/dcn20_optc.c:
display/dc/dcn20/dcn20_optc.c:41: warning: This comment starts with '/**', but isn't a kernel-doc com
drm/amd/display: Fix dc/dcn20/dcn20_optc.c kdoc
Fix all kdoc warnings in dc/dcn20/dcn20_optc.c:
display/dc/dcn20/dcn20_optc.c:41: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC display/dc/dcn20/dcn20_optc.c:76: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst *For the below, I'm not sure how your GSL parameters are stored in your env, display/dc/dcn20/dcn20_optc.c:85: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * There are (MAX_OPTC+1)/2 gsl groups available for use.
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20 |
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#
25879d7b |
| 16-Mar-2023 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Clean FPGA code in dc
[Why] Drop dead code for Linux.
[How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung
drm/amd/display: Clean FPGA code in dc
[Why] Drop dead code for Linux.
[How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71 |
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#
1298d9ab |
| 27-Sep-2022 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Add a missing hook to DCN20
The struct timing_generator_funcs provides a hook for setting up the maximum possible vertical dimension of display for OTG, as the panel supports. DCN10
drm/amd/display: Add a missing hook to DCN20
The struct timing_generator_funcs provides a hook for setting up the maximum possible vertical dimension of display for OTG, as the panel supports. DCN10 has a standard function named optc1_set_vtotal_min_max which all ASICs can use to set the aforementioned hook. Since we did not set it for DCN20, this commit initializes the set_vtotal_min_max with the DCN10 function.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8 |
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#
240e6d25 |
| 08-Dec-2021 |
Isabella Basso <isabbasso@riseup.net> |
drm/amd/display: fix function scopes
This turns previously global functions into static, thus removing compile-time warnings such as:
warning: no previous prototype for 'get_highest_allowed_voltag
drm/amd/display: fix function scopes
This turns previously global functions into static, thus removing compile-time warnings such as:
warning: no previous prototype for 'get_highest_allowed_voltage_level' [-Wmissing-prototypes] 742 | unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ warning: no previous prototype for 'rv1_vbios_smu_send_msg_with_param' [-Wmissing-prototypes] 102 | int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Changes since v1: - As suggested by Rodrigo Siqueira: 1. Rewrite function signatures to make them more readable. 2. Get rid of unused functions in order to remove 'defined but not used' warnings.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Isabella Basso <isabbasso@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1 |
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#
8fa6f4c5 |
| 05-Nov-2021 |
Yi-Ling Chen <Yi-Ling.Chen2@amd.com> |
drm/amd/display: fixed the DSC power off sequence during Driver PnP
[WHY] After unloading driver, driver would not disable DSC function. At next loading driver, driver would power all DSC engines of
drm/amd/display: fixed the DSC power off sequence during Driver PnP
[WHY] After unloading driver, driver would not disable DSC function. At next loading driver, driver would power all DSC engines off. When driver powered the active DSC off, the screen would be gray until reprograming DSC relatived register correcntly.
[HOW] 1. Remove DSC Power down code into init_pipes() 2. Depend on the OTG mapping information and DSC status to skip power off for the working DSC.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5 |
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#
75969362 |
| 15-Sep-2021 |
Ilya <Ilya.Bakoulin@amd.com> |
drm/amd/display: Add PPS immediate update flag for DCN2
[Why] This change is needed for DCN2 to make use of the immediate_update flag. With this flag, update to PPS will be immediate, rather than al
drm/amd/display: Add PPS immediate update flag for DCN2
[Why] This change is needed for DCN2 to make use of the immediate_update flag. With this flag, update to PPS will be immediate, rather than always taking place on dig_update signal.
[How] Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag value.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Ilya <Ilya.Bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52 |
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#
a453d2fa |
| 19-Jul-2021 |
Bing Guo <bing.guo@amd.com> |
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined.
How: Set MASTER_UPDATE_LOCK
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined.
How: Set MASTER_UPDATE_LOCK_DB_X to the value that is adjusted by the number of pipes ODM Combined.
Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
06050a0f |
| 19-Jul-2021 |
Bing Guo <bing.guo@amd.com> |
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined.
How: Set MASTER_UPDATE_LOCK
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined.
How: Set MASTER_UPDATE_LOCK_DB_X to the value that is adjusted by the number of pipes ODM Combined.
Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35 |
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#
5c69cc55 |
| 04-May-2021 |
Jayendran Ramani <Jayendran.Ramani@amd.com> |
drm/amd/display: Return last used DRR VTOTAL from DC
[How] Add call to get the last used VTOTAL from DC
Signed-off-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Anthony Koo <Anthony.
drm/amd/display: Return last used DRR VTOTAL from DC
[How] Add call to get the last used VTOTAL from DC
Signed-off-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31 |
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#
9df857f9 |
| 02-Apr-2020 |
Leo Li <sunpeng.li@amd.com> |
drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10
[Why]
The OTG_VUPDATE_KEEPOUT register and fields is available on DCN10, and named the same in DCN20.
[How]
Move register def
drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10
[Why]
The OTG_VUPDATE_KEEPOUT register and fields is available on DCN10, and named the same in DCN20.
[How]
Move register definition and programming function to dcn10 optc.
There is no functional change.
Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
783bf403 |
| 24-Feb-2021 |
Vladimir Stempen <vladimir.stempen@amd.com> |
drm/amd/display: Fix 64 bit divisions on 32 bit platforms by using div64 API
[why] Synchronization displays with different timings feature uses division operator for 64 bit division, which is not su
drm/amd/display: Fix 64 bit divisions on 32 bit platforms by using div64 API
[why] Synchronization displays with different timings feature uses division operator for 64 bit division, which is not supported by 32 bit platforms
[how] Use div64 API for 64 bit division
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Tested-by: Bindu Ramamurthy<bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
77a2b726 |
| 29-Dec-2020 |
Vladimir Stempen <vladimir.stempen@amd.com> |
drm/amd/display: Synchronize displays with different timings
[why] Vendor based fan noise improvement
[how] Report timing synchronizable when DP streams time frame difference is less than 0.05 per
drm/amd/display: Synchronize displays with different timings
[why] Vendor based fan noise improvement
[how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b42868c |
| 16-Sep-2020 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: Fix OPTC_DATA_FORMAT programming
This should be programmed with timing rather than with odm.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Eryk Brol <ery
drm/amd/display: Fix OPTC_DATA_FORMAT programming
This should be programmed with timing rather than with odm.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dcc8c5fb |
| 19-Jul-2021 |
Bing Guo <bing.guo@amd.com> |
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X
[ Upstream commit 06050a0f01dbac2ca33145ef19a72041206ea983 ]
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by
drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X
[ Upstream commit 06050a0f01dbac2ca33145ef19a72041206ea983 ]
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined.
How: Set MASTER_UPDATE_LOCK_DB_X to the value that is adjusted by the number of pipes ODM Combined.
Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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#
dd7a595a |
| 16-Sep-2020 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: Fix OPTC_DATA_FORMAT programming
This should be programmed with timing rather than with odm.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Eryk Brol <ery
drm/amd/display: Fix OPTC_DATA_FORMAT programming
This should be programmed with timing rather than with odm.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.30, v5.4.29 |
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#
a8665946 |
| 31-Mar-2020 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: add optc get crc support for timings with ODM/DSC
[why] Optc needs to know if timing is enabled with ODM or DSC before computing crc. Otherwise value computed will be inaccurate. B
drm/amd/display: add optc get crc support for timings with ODM/DSC
[why] Optc needs to know if timing is enabled with ODM or DSC before computing crc. Otherwise value computed will be inaccurate. Before this change, the CRC computed without ODM is not equal to the CRC computed with ODM for the same timing. This is unexpected as we are driving the same timing despite of the underlaying hardware setup to achieve it. This is caused by missing hardware programming sequence to support it.
[how] Add the new programming sequence based on hardware guide.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3 |
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#
830806c5 |
| 04-Dec-2019 |
Aric Cyr <aric.cyr@amd.com> |
drm/amd/display: Fix manual trigger source for DCN2
Fix manual trigger source correctly be TRIGA for DCN2 rather than MANUAL_FLOW.
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Ko
drm/amd/display: Fix manual trigger source for DCN2
Fix manual trigger source correctly be TRIGA for DCN2 rather than MANUAL_FLOW.
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.15, v5.4.2, v5.4.1, v5.3.14 |
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#
ec5b356c |
| 26-Nov-2019 |
Nikola Cornij <nikola.cornij@amd.com> |
drm/amd/display: Map ODM memory correctly when doing ODM combine
[why] Up to 4 ODM memory pieces are required per ODM combine and cannot overlap, i.e. each ODM "session" has to use its own memory pi
drm/amd/display: Map ODM memory correctly when doing ODM combine
[why] Up to 4 ODM memory pieces are required per ODM combine and cannot overlap, i.e. each ODM "session" has to use its own memory pieces. The ODM-memory mapping is currently broken for generic case.
The maximum number of memory pieces is ASIC-dependent, but it's always big enough to satisfy maximum number of ODM combines. Memory pieces are mapped as a bit-map, i.e. one memory piece corresponds to one bit. The OPTC doing ODM needs to select memory pieces by setting the corresponding bits, making sure there's no overlap with other OPTC instances that might be doing ODM.
The current mapping works only for OPTC instance indexes smaller than 3. For instance indexes 3 and up it practically maps no ODM memory, causing black, gray or white screen in display configs that include ODM on OPTC instance 3 or up.
[how] Statically map two unique ODM memory pieces for each OPTC instance and piece them together when programming ODM combine mode.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4, v5.3.13, v5.3.12 |
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ad51b4ac |
| 18-Nov-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Extend DMCUB offload testing into dcn20/21
[Why] To quickly validate whether DMCUB is running and accepting commands for offload testing we want to intercept a common sequence as pa
drm/amd/display: Extend DMCUB offload testing into dcn20/21
[Why] To quickly validate whether DMCUB is running and accepting commands for offload testing we want to intercept a common sequence as part of modeset programming.
[How] OTG enable will cause the most impact in terms of golden register changes and it's a single register write.
This approach was previously done in dcn10 code when it was shared with dcn20 but it wasn't ported over to the dcn20 code.
Port over start, execute and wait sequence into dcn20_optc.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.11, v5.3.10, v5.3.9 |
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78c77382 |
| 29-Oct-2019 |
Anthony Koo <Anthony.Koo@amd.com> |
drm/amd/display: cleanup of function pointer tables
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions
[How] 1. Make function pointer table
drm/amd/display: cleanup of function pointer tables
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions
[How] 1. Make function pointer table init in its own init.c file 2. Remove other scenarios in hwseq.c file that need to include headers of other DCN versions. (If needed, it should have been done via the function pointers)
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1da37801 |
| 06-Nov-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
[Why]
DCN2 and DSC are stable enough to be build by default. So drop the flags.
[How]
Remove them using the unifdef tool. The foll
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
[Why]
DCN2 and DSC are stable enough to be build by default. So drop the flags.
[How]
Remove them using the unifdef tool. The following commands were executed in sequence:
$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
In addition:
* Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init()
Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1 |
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93c2340b |
| 17-Sep-2019 |
Martin Leung <martin.leung@amd.com> |
drm/amd/display: add more checks to validate seamless boot timing
[why] we found using an active DP to HDMI panel that we weren't validating dp_pixel_format and hardware timing v_front_porch, causin
drm/amd/display: add more checks to validate seamless boot timing
[why] we found using an active DP to HDMI panel that we weren't validating dp_pixel_format and hardware timing v_front_porch, causing screen to blank and/or corrupt while attempting a seamless boot.
[how] added checks during dc_validate_seamless_boot_timing for these values
Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11 |
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2fef0faa |
| 28-Aug-2019 |
Nikola Cornij <nikola.cornij@amd.com> |
drm/amd/display: Set number of pipes to 1 if the second pipe was disabled
[why] Some ODM-related register settings are inconsistently updated by VBIOS, causing the state in DC to be invalid, which w
drm/amd/display: Set number of pipes to 1 if the second pipe was disabled
[why] Some ODM-related register settings are inconsistently updated by VBIOS, causing the state in DC to be invalid, which would then end up crashing in certain use-cases (such as disable/enable device).
[how] Check the enabled status of the second pipe when determining the number of OPTC sources. If the second pipe is disabled, set the number of sources to 1 regardless of other settings (that may not be updated correctly).
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5 |
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4c3cfe14 |
| 23-May-2019 |
David Francis <David.Francis@amd.com> |
Revert "drm/amd/display: add global master update lock for DCN2"
This reverts commit 6c5be4ac630805d3a3b20157a0c6421ef815fe78.
This commit was accidentally promoted twice
Signed-off-by: David Fran
Revert "drm/amd/display: add global master update lock for DCN2"
This reverts commit 6c5be4ac630805d3a3b20157a0c6421ef815fe78.
This commit was accidentally promoted twice
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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