1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_optc.h" 28 #include "dc.h" 29 30 #define REG(reg)\ 31 optc1->tg_regs->reg 32 33 #define CTX \ 34 optc1->base.ctx 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name 39 40 /** 41 * Enable CRTC 42 * Enable CRTC - call ASIC Control Object to enable Timing generator. 43 */ 44 bool optc2_enable_crtc(struct timing_generator *optc) 45 { 46 /* TODO FPGA wait for answer 47 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 48 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 49 */ 50 struct optc *optc1 = DCN10TG_FROM_TG(optc); 51 52 /* opp instance for OTG. For DCN1.0, ODM is remoed. 53 * OPP and OPTC should 1:1 mapping 54 */ 55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 56 OPTC_SEG0_SRC_SEL, optc->inst); 57 58 /* VTG enable first is for HW workaround */ 59 REG_UPDATE(CONTROL, 60 VTG0_ENABLE, 1); 61 62 REG_SEQ_START(); 63 64 /* Enable CRTC */ 65 REG_UPDATE_2(OTG_CONTROL, 66 OTG_DISABLE_POINT_CNTL, 3, 67 OTG_MASTER_EN, 1); 68 69 REG_SEQ_SUBMIT(); 70 REG_SEQ_WAIT_DONE(); 71 72 return true; 73 } 74 75 /** 76 * DRR double buffering control to select buffer point 77 * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers 78 * Options: anytime, start of frame, dp start of frame (range timing) 79 */ 80 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable) 81 { 82 struct optc *optc1 = DCN10TG_FROM_TG(optc); 83 84 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 85 86 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 87 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable); 88 } 89 90 /** 91 *For the below, I'm not sure how your GSL parameters are stored in your env, 92 * so I will assume a gsl_params struct for now 93 */ 94 void optc2_set_gsl(struct timing_generator *optc, 95 const struct gsl_params *params) 96 { 97 struct optc *optc1 = DCN10TG_FROM_TG(optc); 98 99 /** 100 * There are (MAX_OPTC+1)/2 gsl groups available for use. 101 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1, 102 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves. 103 */ 104 REG_UPDATE_5(OTG_GSL_CONTROL, 105 OTG_GSL0_EN, params->gsl0_en, 106 OTG_GSL1_EN, params->gsl1_en, 107 OTG_GSL2_EN, params->gsl2_en, 108 OTG_GSL_MASTER_EN, params->gsl_master_en, 109 OTG_GSL_MASTER_MODE, params->gsl_master_mode); 110 } 111 112 113 /* Use the gsl allow flip as the master update lock */ 114 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc, 115 const struct gsl_params *params) 116 { 117 struct optc *optc1 = DCN10TG_FROM_TG(optc); 118 119 REG_UPDATE(OTG_GSL_CONTROL, 120 OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en); 121 } 122 123 /* You can control the GSL timing by limiting GSL to a window (X,Y) */ 124 void optc2_set_gsl_window(struct timing_generator *optc, 125 const struct gsl_params *params) 126 { 127 struct optc *optc1 = DCN10TG_FROM_TG(optc); 128 129 REG_SET_2(OTG_GSL_WINDOW_X, 0, 130 OTG_GSL_WINDOW_START_X, params->gsl_window_start_x, 131 OTG_GSL_WINDOW_END_X, params->gsl_window_end_x); 132 REG_SET_2(OTG_GSL_WINDOW_Y, 0, 133 OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y, 134 OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y); 135 } 136 137 void optc2_set_gsl_source_select( 138 struct timing_generator *optc, 139 int group_idx, 140 uint32_t gsl_ready_signal) 141 { 142 struct optc *optc1 = DCN10TG_FROM_TG(optc); 143 144 switch (group_idx) { 145 case 1: 146 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); 147 break; 148 case 2: 149 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); 150 break; 151 case 3: 152 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); 153 break; 154 default: 155 break; 156 } 157 } 158 159 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */ 160 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc, 161 int x_position, 162 int line_num) 163 { 164 struct optc *optc1 = DCN10TG_FROM_TG(optc); 165 166 REG_SET_2(OTG_DSC_START_POSITION, 0, 167 OTG_DSC_START_POSITION_X, x_position, 168 OTG_DSC_START_POSITION_LINE_NUM, line_num); 169 } 170 171 /* Set DSC-related configuration. 172 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 173 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 174 * dsc_slice_width: Slice width in pixels 175 */ 176 void optc2_set_dsc_config(struct timing_generator *optc, 177 enum optc_dsc_mode dsc_mode, 178 uint32_t dsc_bytes_per_pixel, 179 uint32_t dsc_slice_width) 180 { 181 struct optc *optc1 = DCN10TG_FROM_TG(optc); 182 183 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, 184 OPTC_DSC_MODE, dsc_mode); 185 186 REG_SET(OPTC_BYTES_PER_PIXEL, 0, 187 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); 188 189 REG_UPDATE(OPTC_WIDTH_CONTROL, 190 OPTC_DSC_SLICE_WIDTH, dsc_slice_width); 191 } 192 193 /* Get DSC-related configuration. 194 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 195 */ 196 void optc2_get_dsc_status(struct timing_generator *optc, 197 uint32_t *dsc_mode) 198 { 199 struct optc *optc1 = DCN10TG_FROM_TG(optc); 200 201 REG_GET(OPTC_DATA_FORMAT_CONTROL, 202 OPTC_DSC_MODE, dsc_mode); 203 } 204 205 206 /*TEMP: Need to figure out inheritance model here.*/ 207 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 208 { 209 return optc1_is_two_pixels_per_containter(timing); 210 } 211 212 void optc2_set_odm_bypass(struct timing_generator *optc, 213 const struct dc_crtc_timing *dc_crtc_timing) 214 { 215 struct optc *optc1 = DCN10TG_FROM_TG(optc); 216 uint32_t h_div_2 = 0; 217 218 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 219 OPTC_NUM_OF_INPUT_SEGMENT, 0, 220 OPTC_SEG0_SRC_SEL, optc->inst, 221 OPTC_SEG1_SRC_SEL, 0xf); 222 REG_WRITE(OTG_H_TIMING_CNTL, 0); 223 224 h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing); 225 REG_UPDATE(OTG_H_TIMING_CNTL, 226 OTG_H_TIMING_DIV_BY2, h_div_2); 227 REG_SET(OPTC_MEMORY_CONFIG, 0, 228 OPTC_MEM_SEL, 0); 229 optc1->opp_count = 1; 230 } 231 232 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 233 struct dc_crtc_timing *timing) 234 { 235 struct optc *optc1 = DCN10TG_FROM_TG(optc); 236 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 237 / opp_cnt; 238 uint32_t memory_mask; 239 240 ASSERT(opp_cnt == 2); 241 242 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic 243 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); 244 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start 245 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0, 246 * MASTER_UPDATE_LOCK_DB_X, 160, 247 * MASTER_UPDATE_LOCK_DB_Y, 240); 248 */ 249 250 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192, 251 * however, for ODM combine we can simplify by always using 4. 252 * To make sure there's no overlap, each instance "reserves" 2 memories and 253 * they are uniquely combined here. 254 */ 255 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 256 257 if (REG(OPTC_MEMORY_CONFIG)) 258 REG_SET(OPTC_MEMORY_CONFIG, 0, 259 OPTC_MEM_SEL, memory_mask); 260 261 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 262 OPTC_NUM_OF_INPUT_SEGMENT, 1, 263 OPTC_SEG0_SRC_SEL, opp_id[0], 264 OPTC_SEG1_SRC_SEL, opp_id[1]); 265 266 REG_UPDATE(OPTC_WIDTH_CONTROL, 267 OPTC_SEGMENT_WIDTH, mpcc_hactive); 268 269 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); 270 optc1->opp_count = opp_cnt; 271 } 272 273 void optc2_get_optc_source(struct timing_generator *optc, 274 uint32_t *num_of_src_opp, 275 uint32_t *src_opp_id_0, 276 uint32_t *src_opp_id_1) 277 { 278 uint32_t num_of_input_segments; 279 struct optc *optc1 = DCN10TG_FROM_TG(optc); 280 281 REG_GET_3(OPTC_DATA_SOURCE_SELECT, 282 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments, 283 OPTC_SEG0_SRC_SEL, src_opp_id_0, 284 OPTC_SEG1_SRC_SEL, src_opp_id_1); 285 286 if (num_of_input_segments == 1) 287 *num_of_src_opp = 2; 288 else 289 *num_of_src_opp = 1; 290 291 /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */ 292 if (*src_opp_id_1 == 0xf) 293 *num_of_src_opp = 1; 294 } 295 296 void optc2_set_dwb_source(struct timing_generator *optc, 297 uint32_t dwb_pipe_inst) 298 { 299 struct optc *optc1 = DCN10TG_FROM_TG(optc); 300 301 if (dwb_pipe_inst == 0) 302 REG_UPDATE(DWB_SOURCE_SELECT, 303 OPTC_DWB0_SOURCE_SELECT, optc->inst); 304 else if (dwb_pipe_inst == 1) 305 REG_UPDATE(DWB_SOURCE_SELECT, 306 OPTC_DWB1_SOURCE_SELECT, optc->inst); 307 } 308 309 void optc2_align_vblanks( 310 struct timing_generator *optc_master, 311 struct timing_generator *optc_slave, 312 uint32_t master_pixel_clock_100Hz, 313 uint32_t slave_pixel_clock_100Hz, 314 uint8_t master_clock_divider, 315 uint8_t slave_clock_divider) 316 { 317 /* accessing slave OTG registers */ 318 struct optc *optc1 = DCN10TG_FROM_TG(optc_slave); 319 320 uint32_t master_v_active = 0; 321 uint32_t master_h_total = 0; 322 uint32_t slave_h_total = 0; 323 uint64_t L, XY; 324 uint32_t X, Y, p = 10000; 325 uint32_t master_update_lock; 326 327 /* disable slave OTG */ 328 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); 329 /* wait until disabled */ 330 REG_WAIT(OTG_CONTROL, 331 OTG_CURRENT_MASTER_EN_STATE, 332 0, 10, 5000); 333 334 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); 335 336 /* assign slave OTG to be controlled by master update lock */ 337 REG_SET(OTG_GLOBAL_CONTROL0, 0, 338 OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst); 339 340 /* accessing master OTG registers */ 341 optc1 = DCN10TG_FROM_TG(optc_master); 342 343 /* saving update lock state, not sure if it's needed */ 344 REG_GET(OTG_MASTER_UPDATE_LOCK, 345 OTG_MASTER_UPDATE_LOCK, &master_update_lock); 346 /* unlocking master OTG */ 347 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 348 OTG_MASTER_UPDATE_LOCK, 0); 349 350 REG_GET(OTG_V_BLANK_START_END, 351 OTG_V_BLANK_START, &master_v_active); 352 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); 353 354 /* calculate when to enable slave OTG */ 355 L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz; 356 L = div_u64(L, master_h_total); 357 L = div_u64(L, slave_pixel_clock_100Hz); 358 XY = div_u64(L, p); 359 Y = master_v_active - XY - 1; 360 X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); 361 362 /* 363 * set master OTG to unlock when V/H 364 * counters reach calculated values 365 */ 366 REG_UPDATE(OTG_GLOBAL_CONTROL1, 367 MASTER_UPDATE_LOCK_DB_EN, 1); 368 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 369 MASTER_UPDATE_LOCK_DB_X, 370 X, 371 MASTER_UPDATE_LOCK_DB_Y, 372 Y); 373 374 /* lock master OTG */ 375 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 376 OTG_MASTER_UPDATE_LOCK, 1); 377 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 378 UPDATE_LOCK_STATUS, 1, 1, 10); 379 380 /* accessing slave OTG registers */ 381 optc1 = DCN10TG_FROM_TG(optc_slave); 382 383 /* 384 * enable slave OTG, the OTG is locked with 385 * master's update lock, so it will not run 386 */ 387 REG_UPDATE(OTG_CONTROL, 388 OTG_MASTER_EN, 1); 389 390 /* accessing master OTG registers */ 391 optc1 = DCN10TG_FROM_TG(optc_master); 392 393 /* 394 * unlock master OTG. When master H/V counters reach 395 * DB_XY point, slave OTG will start 396 */ 397 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 398 OTG_MASTER_UPDATE_LOCK, 0); 399 400 /* accessing slave OTG registers */ 401 optc1 = DCN10TG_FROM_TG(optc_slave); 402 403 /* wait for slave OTG to start running*/ 404 REG_WAIT(OTG_CONTROL, 405 OTG_CURRENT_MASTER_EN_STATE, 406 1, 10, 5000); 407 408 /* accessing master OTG registers */ 409 optc1 = DCN10TG_FROM_TG(optc_master); 410 411 /* disable the XY point*/ 412 REG_UPDATE(OTG_GLOBAL_CONTROL1, 413 MASTER_UPDATE_LOCK_DB_EN, 0); 414 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 415 MASTER_UPDATE_LOCK_DB_X, 416 0, 417 MASTER_UPDATE_LOCK_DB_Y, 418 0); 419 420 /*restore master update lock*/ 421 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 422 OTG_MASTER_UPDATE_LOCK, master_update_lock); 423 424 /* accessing slave OTG registers */ 425 optc1 = DCN10TG_FROM_TG(optc_slave); 426 /* restore slave to be controlled by it's own */ 427 REG_SET(OTG_GLOBAL_CONTROL0, 0, 428 OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst); 429 430 } 431 432 void optc2_triplebuffer_lock(struct timing_generator *optc) 433 { 434 struct optc *optc1 = DCN10TG_FROM_TG(optc); 435 436 REG_SET(OTG_GLOBAL_CONTROL0, 0, 437 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 438 439 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 440 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 441 442 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 443 OTG_MASTER_UPDATE_LOCK, 1); 444 445 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 446 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 447 UPDATE_LOCK_STATUS, 1, 448 1, 10); 449 } 450 451 void optc2_triplebuffer_unlock(struct timing_generator *optc) 452 { 453 struct optc *optc1 = DCN10TG_FROM_TG(optc); 454 455 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 456 OTG_MASTER_UPDATE_LOCK, 0); 457 458 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 459 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0); 460 461 } 462 463 void optc2_lock_doublebuffer_enable(struct timing_generator *optc) 464 { 465 struct optc *optc1 = DCN10TG_FROM_TG(optc); 466 uint32_t v_blank_start = 0; 467 uint32_t h_blank_start = 0; 468 469 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1); 470 471 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, 472 DIG_UPDATE_LOCATION, 20); 473 474 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); 475 476 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); 477 478 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 479 MASTER_UPDATE_LOCK_DB_X, 480 (h_blank_start - 200 - 1) / optc1->opp_count, 481 MASTER_UPDATE_LOCK_DB_Y, 482 v_blank_start - 1); 483 484 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, 485 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0, 486 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100, 487 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 488 } 489 490 void optc2_lock_doublebuffer_disable(struct timing_generator *optc) 491 { 492 struct optc *optc1 = DCN10TG_FROM_TG(optc); 493 494 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 495 MASTER_UPDATE_LOCK_DB_X, 496 0, 497 MASTER_UPDATE_LOCK_DB_Y, 498 0); 499 500 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, 501 DIG_UPDATE_LOCATION, 0); 502 503 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0); 504 } 505 506 void optc2_setup_manual_trigger(struct timing_generator *optc) 507 { 508 struct optc *optc1 = DCN10TG_FROM_TG(optc); 509 510 REG_SET_8(OTG_TRIGA_CNTL, 0, 511 OTG_TRIGA_SOURCE_SELECT, 21, 512 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 513 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 514 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 515 OTG_TRIGA_POLARITY_SELECT, 0, 516 OTG_TRIGA_FREQUENCY_SELECT, 0, 517 OTG_TRIGA_DELAY, 0, 518 OTG_TRIGA_CLEAR, 1); 519 } 520 521 void optc2_program_manual_trigger(struct timing_generator *optc) 522 { 523 struct optc *optc1 = DCN10TG_FROM_TG(optc); 524 525 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, 526 OTG_TRIGA_MANUAL_TRIG, 1); 527 } 528 529 bool optc2_configure_crc(struct timing_generator *optc, 530 const struct crc_params *params) 531 { 532 struct optc *optc1 = DCN10TG_FROM_TG(optc); 533 534 REG_SET_2(OTG_CRC_CNTL2, 0, 535 OTG_CRC_DSC_MODE, params->dsc_mode, 536 OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); 537 538 return optc1_configure_crc(optc, params); 539 } 540 541 542 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate) 543 { 544 struct optc *optc1 = DCN10TG_FROM_TG(optc); 545 546 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); 547 } 548 549 static struct timing_generator_funcs dcn20_tg_funcs = { 550 .validate_timing = optc1_validate_timing, 551 .program_timing = optc1_program_timing, 552 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 553 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 554 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 555 .program_global_sync = optc1_program_global_sync, 556 .enable_crtc = optc2_enable_crtc, 557 .disable_crtc = optc1_disable_crtc, 558 /* used by enable_timing_synchronization. Not need for FPGA */ 559 .is_counter_moving = optc1_is_counter_moving, 560 .get_position = optc1_get_position, 561 .get_frame_count = optc1_get_vblank_counter, 562 .get_scanoutpos = optc1_get_crtc_scanoutpos, 563 .get_otg_active_size = optc1_get_otg_active_size, 564 .set_early_control = optc1_set_early_control, 565 /* used by enable_timing_synchronization. Not need for FPGA */ 566 .wait_for_state = optc1_wait_for_state, 567 .set_blank = optc1_set_blank, 568 .is_blanked = optc1_is_blanked, 569 .set_blank_color = optc1_program_blank_color, 570 .enable_reset_trigger = optc1_enable_reset_trigger, 571 .enable_crtc_reset = optc1_enable_crtc_reset, 572 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 573 .triplebuffer_lock = optc2_triplebuffer_lock, 574 .triplebuffer_unlock = optc2_triplebuffer_unlock, 575 .disable_reset_trigger = optc1_disable_reset_trigger, 576 .lock = optc1_lock, 577 .unlock = optc1_unlock, 578 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable, 579 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable, 580 .enable_optc_clock = optc1_enable_optc_clock, 581 .set_drr = optc1_set_drr, 582 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 583 .set_static_screen_control = optc1_set_static_screen_control, 584 .program_stereo = optc1_program_stereo, 585 .is_stereo_left_eye = optc1_is_stereo_left_eye, 586 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 587 .tg_init = optc1_tg_init, 588 .is_tg_enabled = optc1_is_tg_enabled, 589 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 590 .clear_optc_underflow = optc1_clear_optc_underflow, 591 .setup_global_swap_lock = NULL, 592 .get_crc = optc1_get_crc, 593 .configure_crc = optc2_configure_crc, 594 .set_dsc_config = optc2_set_dsc_config, 595 .get_dsc_status = optc2_get_dsc_status, 596 .set_dwb_source = optc2_set_dwb_source, 597 .set_odm_bypass = optc2_set_odm_bypass, 598 .set_odm_combine = optc2_set_odm_combine, 599 .get_optc_source = optc2_get_optc_source, 600 .set_gsl = optc2_set_gsl, 601 .set_gsl_source_select = optc2_set_gsl_source_select, 602 .set_vtg_params = optc1_set_vtg_params, 603 .program_manual_trigger = optc2_program_manual_trigger, 604 .setup_manual_trigger = optc2_setup_manual_trigger, 605 .get_hw_timing = optc1_get_hw_timing, 606 .align_vblanks = optc2_align_vblanks, 607 }; 608 609 void dcn20_timing_generator_init(struct optc *optc1) 610 { 611 optc1->base.funcs = &dcn20_tg_funcs; 612 613 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 614 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 615 616 optc1->min_h_blank = 32; 617 optc1->min_v_blank = 3; 618 optc1->min_v_blank_interlace = 5; 619 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. 620 optc1->min_v_sync_width = 1; 621 } 622