1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_optc.h" 28 #include "dc.h" 29 30 #define REG(reg)\ 31 optc1->tg_regs->reg 32 33 #define CTX \ 34 optc1->base.ctx 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name 39 40 /** 41 * Enable CRTC 42 * Enable CRTC - call ASIC Control Object to enable Timing generator. 43 */ 44 bool optc2_enable_crtc(struct timing_generator *optc) 45 { 46 /* TODO FPGA wait for answer 47 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 48 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 49 */ 50 struct optc *optc1 = DCN10TG_FROM_TG(optc); 51 52 /* opp instance for OTG. For DCN1.0, ODM is remoed. 53 * OPP and OPTC should 1:1 mapping 54 */ 55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 56 OPTC_SEG0_SRC_SEL, optc->inst); 57 58 /* VTG enable first is for HW workaround */ 59 REG_UPDATE(CONTROL, 60 VTG0_ENABLE, 1); 61 62 /* Enable CRTC */ 63 REG_UPDATE_2(OTG_CONTROL, 64 OTG_DISABLE_POINT_CNTL, 3, 65 OTG_MASTER_EN, 1); 66 67 return true; 68 } 69 70 /** 71 * DRR double buffering control to select buffer point 72 * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers 73 * Options: anytime, start of frame, dp start of frame (range timing) 74 */ 75 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable) 76 { 77 struct optc *optc1 = DCN10TG_FROM_TG(optc); 78 79 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 80 81 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 82 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable); 83 } 84 85 /** 86 *For the below, I'm not sure how your GSL parameters are stored in your env, 87 * so I will assume a gsl_params struct for now 88 */ 89 void optc2_set_gsl(struct timing_generator *optc, 90 const struct gsl_params *params) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 /** 95 * There are (MAX_OPTC+1)/2 gsl groups available for use. 96 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1, 97 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves. 98 */ 99 REG_UPDATE_5(OTG_GSL_CONTROL, 100 OTG_GSL0_EN, params->gsl0_en, 101 OTG_GSL1_EN, params->gsl1_en, 102 OTG_GSL2_EN, params->gsl2_en, 103 OTG_GSL_MASTER_EN, params->gsl_master_en, 104 OTG_GSL_MASTER_MODE, params->gsl_master_mode); 105 } 106 107 108 /* Use the gsl allow flip as the master update lock */ 109 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc, 110 const struct gsl_params *params) 111 { 112 struct optc *optc1 = DCN10TG_FROM_TG(optc); 113 114 REG_UPDATE(OTG_GSL_CONTROL, 115 OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en); 116 } 117 118 /* You can control the GSL timing by limiting GSL to a window (X,Y) */ 119 void optc2_set_gsl_window(struct timing_generator *optc, 120 const struct gsl_params *params) 121 { 122 struct optc *optc1 = DCN10TG_FROM_TG(optc); 123 124 REG_SET_2(OTG_GSL_WINDOW_X, 0, 125 OTG_GSL_WINDOW_START_X, params->gsl_window_start_x, 126 OTG_GSL_WINDOW_END_X, params->gsl_window_end_x); 127 REG_SET_2(OTG_GSL_WINDOW_Y, 0, 128 OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y, 129 OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y); 130 } 131 132 /** 133 * Vupdate keepout can be set to a window to block the update lock for that pipe from changing. 134 * Start offset begins with vstartup and goes for x number of clocks, 135 * end offset starts from end of vupdate to x number of clocks. 136 */ 137 void optc2_set_vupdate_keepout(struct timing_generator *optc, 138 const struct vupdate_keepout_params *params) 139 { 140 struct optc *optc1 = DCN10TG_FROM_TG(optc); 141 142 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, 143 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset, 144 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset, 145 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable); 146 } 147 148 void optc2_set_gsl_source_select( 149 struct timing_generator *optc, 150 int group_idx, 151 uint32_t gsl_ready_signal) 152 { 153 struct optc *optc1 = DCN10TG_FROM_TG(optc); 154 155 switch (group_idx) { 156 case 1: 157 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); 158 break; 159 case 2: 160 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); 161 break; 162 case 3: 163 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); 164 break; 165 default: 166 break; 167 } 168 } 169 170 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 171 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */ 172 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc, 173 int x_position, 174 int line_num) 175 { 176 struct optc *optc1 = DCN10TG_FROM_TG(optc); 177 178 REG_SET_2(OTG_DSC_START_POSITION, 0, 179 OTG_DSC_START_POSITION_X, x_position, 180 OTG_DSC_START_POSITION_LINE_NUM, line_num); 181 } 182 183 /* Set DSC-related configuration. 184 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 185 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 186 * dsc_slice_width: Slice width in pixels 187 */ 188 void optc2_set_dsc_config(struct timing_generator *optc, 189 enum optc_dsc_mode dsc_mode, 190 uint32_t dsc_bytes_per_pixel, 191 uint32_t dsc_slice_width) 192 { 193 struct optc *optc1 = DCN10TG_FROM_TG(optc); 194 195 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, 196 OPTC_DSC_MODE, dsc_mode); 197 198 REG_SET(OPTC_BYTES_PER_PIXEL, 0, 199 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); 200 201 REG_UPDATE(OPTC_WIDTH_CONTROL, 202 OPTC_DSC_SLICE_WIDTH, dsc_slice_width); 203 } 204 #endif 205 206 /** 207 * PTI i think is already done somewhere else for 2ka 208 * (opp?, please double check. 209 * OPTC side only has 1 register to set for PTI_ENABLE) 210 */ 211 212 void optc2_set_odm_bypass(struct timing_generator *optc, 213 const struct dc_crtc_timing *dc_crtc_timing) 214 { 215 struct optc *optc1 = DCN10TG_FROM_TG(optc); 216 uint32_t h_div_2 = 0; 217 218 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 219 OPTC_NUM_OF_INPUT_SEGMENT, 0, 220 OPTC_SEG0_SRC_SEL, optc->inst, 221 OPTC_SEG1_SRC_SEL, 0xf); 222 REG_WRITE(OTG_H_TIMING_CNTL, 0); 223 224 h_div_2 = optc1_is_two_pixels_per_containter(dc_crtc_timing); 225 REG_UPDATE(OTG_H_TIMING_CNTL, 226 OTG_H_TIMING_DIV_BY2, h_div_2); 227 REG_SET(OPTC_MEMORY_CONFIG, 0, 228 OPTC_MEM_SEL, 0); 229 optc1->opp_count = 1; 230 } 231 232 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 233 struct dc_crtc_timing *timing) 234 { 235 struct optc *optc1 = DCN10TG_FROM_TG(optc); 236 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */ 237 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 238 / opp_cnt; 239 int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf; 240 uint32_t data_fmt = 0; 241 242 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic 243 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); 244 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start 245 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0, 246 * MASTER_UPDATE_LOCK_DB_X, 160, 247 * MASTER_UPDATE_LOCK_DB_Y, 240); 248 */ 249 if (REG(OPTC_MEMORY_CONFIG)) 250 REG_SET(OPTC_MEMORY_CONFIG, 0, 251 OPTC_MEM_SEL, memory_mask << (optc->inst * 4)); 252 253 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 254 data_fmt = 1; 255 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 256 data_fmt = 2; 257 258 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 259 260 ASSERT(opp_cnt == 2); 261 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 262 OPTC_NUM_OF_INPUT_SEGMENT, 1, 263 OPTC_SEG0_SRC_SEL, opp_id[0], 264 OPTC_SEG1_SRC_SEL, opp_id[1]); 265 266 REG_UPDATE(OPTC_WIDTH_CONTROL, 267 OPTC_SEGMENT_WIDTH, mpcc_hactive); 268 269 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); 270 optc1->opp_count = opp_cnt; 271 } 272 273 void optc2_get_optc_source(struct timing_generator *optc, 274 uint32_t *num_of_src_opp, 275 uint32_t *src_opp_id_0, 276 uint32_t *src_opp_id_1) 277 { 278 uint32_t num_of_input_segments; 279 struct optc *optc1 = DCN10TG_FROM_TG(optc); 280 281 REG_GET_3(OPTC_DATA_SOURCE_SELECT, 282 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments, 283 OPTC_SEG0_SRC_SEL, src_opp_id_0, 284 OPTC_SEG1_SRC_SEL, src_opp_id_1); 285 286 if (num_of_input_segments == 1) 287 *num_of_src_opp = 2; 288 else 289 *num_of_src_opp = 1; 290 } 291 292 void optc2_set_dwb_source(struct timing_generator *optc, 293 uint32_t dwb_pipe_inst) 294 { 295 struct optc *optc1 = DCN10TG_FROM_TG(optc); 296 297 if (dwb_pipe_inst == 0) 298 REG_UPDATE(DWB_SOURCE_SELECT, 299 OPTC_DWB0_SOURCE_SELECT, optc->inst); 300 else if (dwb_pipe_inst == 1) 301 REG_UPDATE(DWB_SOURCE_SELECT, 302 OPTC_DWB1_SOURCE_SELECT, optc->inst); 303 } 304 305 void optc2_triplebuffer_lock(struct timing_generator *optc) 306 { 307 struct optc *optc1 = DCN10TG_FROM_TG(optc); 308 309 REG_SET(OTG_GLOBAL_CONTROL0, 0, 310 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 311 312 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 313 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 314 315 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 316 OTG_MASTER_UPDATE_LOCK, 1); 317 318 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 319 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 320 UPDATE_LOCK_STATUS, 1, 321 1, 10); 322 } 323 324 void optc2_triplebuffer_unlock(struct timing_generator *optc) 325 { 326 struct optc *optc1 = DCN10TG_FROM_TG(optc); 327 328 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 329 OTG_MASTER_UPDATE_LOCK, 0); 330 331 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 332 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0); 333 334 } 335 336 void optc2_lock_doublebuffer_enable(struct timing_generator *optc) 337 { 338 struct optc *optc1 = DCN10TG_FROM_TG(optc); 339 uint32_t v_blank_start = 0; 340 uint32_t h_blank_start = 0; 341 342 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1); 343 344 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, 345 DIG_UPDATE_LOCATION, 20); 346 347 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); 348 349 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); 350 351 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 352 MASTER_UPDATE_LOCK_DB_X, 353 h_blank_start - 200 - 1, 354 MASTER_UPDATE_LOCK_DB_Y, 355 v_blank_start - 1); 356 } 357 358 void optc2_lock_doublebuffer_disable(struct timing_generator *optc) 359 { 360 struct optc *optc1 = DCN10TG_FROM_TG(optc); 361 362 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 363 MASTER_UPDATE_LOCK_DB_X, 364 0, 365 MASTER_UPDATE_LOCK_DB_Y, 366 0); 367 368 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, 369 DIG_UPDATE_LOCATION, 0); 370 371 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0); 372 } 373 374 void optc2_setup_manual_trigger(struct timing_generator *optc) 375 { 376 struct optc *optc1 = DCN10TG_FROM_TG(optc); 377 378 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 379 MANUAL_FLOW_CONTROL, 1); 380 381 REG_SET(OTG_GLOBAL_CONTROL2, 0, 382 MANUAL_FLOW_CONTROL_SEL, optc->inst); 383 384 REG_SET_8(OTG_TRIGA_CNTL, 0, 385 OTG_TRIGA_SOURCE_SELECT, 22, 386 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 387 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 388 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 389 OTG_TRIGA_POLARITY_SELECT, 0, 390 OTG_TRIGA_FREQUENCY_SELECT, 0, 391 OTG_TRIGA_DELAY, 0, 392 OTG_TRIGA_CLEAR, 1); 393 } 394 395 void optc2_program_manual_trigger(struct timing_generator *optc) 396 { 397 struct optc *optc1 = DCN10TG_FROM_TG(optc); 398 399 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, 400 OTG_TRIGA_MANUAL_TRIG, 1); 401 } 402 403 static struct timing_generator_funcs dcn20_tg_funcs = { 404 .validate_timing = optc1_validate_timing, 405 .program_timing = optc1_program_timing, 406 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 407 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 408 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 409 .program_global_sync = optc1_program_global_sync, 410 .enable_crtc = optc2_enable_crtc, 411 .disable_crtc = optc1_disable_crtc, 412 /* used by enable_timing_synchronization. Not need for FPGA */ 413 .is_counter_moving = optc1_is_counter_moving, 414 .get_position = optc1_get_position, 415 .get_frame_count = optc1_get_vblank_counter, 416 .get_scanoutpos = optc1_get_crtc_scanoutpos, 417 .get_otg_active_size = optc1_get_otg_active_size, 418 .set_early_control = optc1_set_early_control, 419 /* used by enable_timing_synchronization. Not need for FPGA */ 420 .wait_for_state = optc1_wait_for_state, 421 .set_blank = optc1_set_blank, 422 .is_blanked = optc1_is_blanked, 423 .set_blank_color = optc1_program_blank_color, 424 .enable_reset_trigger = optc1_enable_reset_trigger, 425 .enable_crtc_reset = optc1_enable_crtc_reset, 426 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 427 .triplebuffer_lock = optc2_triplebuffer_lock, 428 .triplebuffer_unlock = optc2_triplebuffer_unlock, 429 .disable_reset_trigger = optc1_disable_reset_trigger, 430 .lock = optc1_lock, 431 .unlock = optc1_unlock, 432 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable, 433 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable, 434 .enable_optc_clock = optc1_enable_optc_clock, 435 .set_drr = optc1_set_drr, 436 .set_static_screen_control = optc1_set_static_screen_control, 437 .program_stereo = optc1_program_stereo, 438 .is_stereo_left_eye = optc1_is_stereo_left_eye, 439 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 440 .tg_init = optc1_tg_init, 441 .is_tg_enabled = optc1_is_tg_enabled, 442 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 443 .clear_optc_underflow = optc1_clear_optc_underflow, 444 .setup_global_swap_lock = NULL, 445 .get_crc = optc1_get_crc, 446 .configure_crc = optc1_configure_crc, 447 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 448 .set_dsc_config = optc2_set_dsc_config, 449 #endif 450 .set_dwb_source = optc2_set_dwb_source, 451 .set_odm_bypass = optc2_set_odm_bypass, 452 .set_odm_combine = optc2_set_odm_combine, 453 .get_optc_source = optc2_get_optc_source, 454 .set_gsl = optc2_set_gsl, 455 .set_gsl_source_select = optc2_set_gsl_source_select, 456 .set_vtg_params = optc1_set_vtg_params, 457 .program_manual_trigger = optc2_program_manual_trigger, 458 .setup_manual_trigger = optc2_setup_manual_trigger, 459 .is_matching_timing = optc1_is_matching_timing 460 }; 461 462 void dcn20_timing_generator_init(struct optc *optc1) 463 { 464 optc1->base.funcs = &dcn20_tg_funcs; 465 466 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 467 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 468 469 optc1->min_h_blank = 32; 470 optc1->min_v_blank = 3; 471 optc1->min_v_blank_interlace = 5; 472 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. 473 optc1->min_v_sync_width = 1; 474 } 475 476