1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "reg_helper.h"
27 #include "dcn20_optc.h"
28 #include "dc.h"
29 
30 #define REG(reg)\
31 	optc1->tg_regs->reg
32 
33 #define CTX \
34 	optc1->base.ctx
35 
36 #undef FN
37 #define FN(reg_name, field_name) \
38 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
39 
40 /**
41  * Enable CRTC
42  * Enable CRTC - call ASIC Control Object to enable Timing generator.
43  */
44 bool optc2_enable_crtc(struct timing_generator *optc)
45 {
46 	/* TODO FPGA wait for answer
47 	 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
48 	 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
49 	 */
50 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
51 
52 	/* opp instance for OTG. For DCN1.0, ODM is remoed.
53 	 * OPP and OPTC should 1:1 mapping
54 	 */
55 	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
56 			OPTC_SEG0_SRC_SEL, optc->inst);
57 
58 	/* VTG enable first is for HW workaround */
59 	REG_UPDATE(CONTROL,
60 			VTG0_ENABLE, 1);
61 
62 	REG_SEQ_START();
63 
64 	/* Enable CRTC */
65 	REG_UPDATE_2(OTG_CONTROL,
66 			OTG_DISABLE_POINT_CNTL, 3,
67 			OTG_MASTER_EN, 1);
68 
69 	REG_SEQ_SUBMIT();
70 	REG_SEQ_WAIT_DONE();
71 
72 	return true;
73 }
74 
75 /**
76  * DRR double buffering control to select buffer point
77  * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers
78  * Options: anytime, start of frame, dp start of frame (range timing)
79  */
80 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
81 {
82 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
83 
84 	uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
85 
86 	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
87 		OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable);
88 }
89 
90 /**
91  *For the below, I'm not sure how your GSL parameters are stored in your env,
92  * so I will assume a gsl_params struct for now
93  */
94 void optc2_set_gsl(struct timing_generator *optc,
95 		   const struct gsl_params *params)
96 {
97 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
98 
99 /**
100  * There are (MAX_OPTC+1)/2 gsl groups available for use.
101  * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
102  * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
103  */
104 	REG_UPDATE_5(OTG_GSL_CONTROL,
105 		OTG_GSL0_EN, params->gsl0_en,
106 		OTG_GSL1_EN, params->gsl1_en,
107 		OTG_GSL2_EN, params->gsl2_en,
108 		OTG_GSL_MASTER_EN, params->gsl_master_en,
109 		OTG_GSL_MASTER_MODE, params->gsl_master_mode);
110 }
111 
112 
113 /* Use the gsl allow flip as the master update lock */
114 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
115 		   const struct gsl_params *params)
116 {
117 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
118 
119 	REG_UPDATE(OTG_GSL_CONTROL,
120 		OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en);
121 }
122 
123 /* You can control the GSL timing by limiting GSL to a window (X,Y) */
124 void optc2_set_gsl_window(struct timing_generator *optc,
125 		   const struct gsl_params *params)
126 {
127 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
128 
129 	REG_SET_2(OTG_GSL_WINDOW_X, 0,
130 		OTG_GSL_WINDOW_START_X, params->gsl_window_start_x,
131 		OTG_GSL_WINDOW_END_X, params->gsl_window_end_x);
132 	REG_SET_2(OTG_GSL_WINDOW_Y, 0,
133 		OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y,
134 		OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
135 }
136 
137 void optc2_set_gsl_source_select(
138 		struct timing_generator *optc,
139 		int group_idx,
140 		uint32_t gsl_ready_signal)
141 {
142 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
143 
144 	switch (group_idx) {
145 	case 1:
146 		REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
147 		break;
148 	case 2:
149 		REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
150 		break;
151 	case 3:
152 		REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
153 		break;
154 	default:
155 		break;
156 	}
157 }
158 
159 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
160 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
161 					int x_position,
162 					int line_num)
163 {
164 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
165 
166 	REG_SET_2(OTG_DSC_START_POSITION, 0,
167 			OTG_DSC_START_POSITION_X, x_position,
168 			OTG_DSC_START_POSITION_LINE_NUM, line_num);
169 }
170 
171 /* Set DSC-related configuration.
172  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
173  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
174  *   dsc_slice_width: Slice width in pixels
175  */
176 void optc2_set_dsc_config(struct timing_generator *optc,
177 					enum optc_dsc_mode dsc_mode,
178 					uint32_t dsc_bytes_per_pixel,
179 					uint32_t dsc_slice_width)
180 {
181 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
182 
183 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
184 		OPTC_DSC_MODE, dsc_mode);
185 
186 	REG_SET(OPTC_BYTES_PER_PIXEL, 0,
187 		OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
188 
189 	REG_UPDATE(OPTC_WIDTH_CONTROL,
190 		OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
191 }
192 
193 /*TEMP: Need to figure out inheritance model here.*/
194 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
195 {
196 	return optc1_is_two_pixels_per_containter(timing);
197 }
198 
199 void optc2_set_odm_bypass(struct timing_generator *optc,
200 		const struct dc_crtc_timing *dc_crtc_timing)
201 {
202 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
203 	uint32_t h_div_2 = 0;
204 
205 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
206 			OPTC_NUM_OF_INPUT_SEGMENT, 0,
207 			OPTC_SEG0_SRC_SEL, optc->inst,
208 			OPTC_SEG1_SRC_SEL, 0xf);
209 	REG_WRITE(OTG_H_TIMING_CNTL, 0);
210 
211 	h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
212 	REG_UPDATE(OTG_H_TIMING_CNTL,
213 			OTG_H_TIMING_DIV_BY2, h_div_2);
214 	REG_SET(OPTC_MEMORY_CONFIG, 0,
215 			OPTC_MEM_SEL, 0);
216 	optc1->opp_count = 1;
217 }
218 
219 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
220 		struct dc_crtc_timing *timing)
221 {
222 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
223 	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
224 			/ opp_cnt;
225 	uint32_t memory_mask;
226 
227 	ASSERT(opp_cnt == 2);
228 
229 	/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
230 	 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
231 	 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
232 	 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
233 	 *		MASTER_UPDATE_LOCK_DB_X, 160,
234 	 *		MASTER_UPDATE_LOCK_DB_Y, 240);
235 	 */
236 
237 	/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
238 	 * however, for ODM combine we can simplify by always using 4.
239 	 * To make sure there's no overlap, each instance "reserves" 2 memories and
240 	 * they are uniquely combined here.
241 	 */
242 	memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
243 
244 	if (REG(OPTC_MEMORY_CONFIG))
245 		REG_SET(OPTC_MEMORY_CONFIG, 0,
246 			OPTC_MEM_SEL, memory_mask);
247 
248 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
249 			OPTC_NUM_OF_INPUT_SEGMENT, 1,
250 			OPTC_SEG0_SRC_SEL, opp_id[0],
251 			OPTC_SEG1_SRC_SEL, opp_id[1]);
252 
253 	REG_UPDATE(OPTC_WIDTH_CONTROL,
254 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
255 
256 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
257 	optc1->opp_count = opp_cnt;
258 }
259 
260 void optc2_get_optc_source(struct timing_generator *optc,
261 		uint32_t *num_of_src_opp,
262 		uint32_t *src_opp_id_0,
263 		uint32_t *src_opp_id_1)
264 {
265 	uint32_t num_of_input_segments;
266 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
267 
268 	REG_GET_3(OPTC_DATA_SOURCE_SELECT,
269 			OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
270 			OPTC_SEG0_SRC_SEL, src_opp_id_0,
271 			OPTC_SEG1_SRC_SEL, src_opp_id_1);
272 
273 	if (num_of_input_segments == 1)
274 		*num_of_src_opp = 2;
275 	else
276 		*num_of_src_opp = 1;
277 
278 	/* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
279 	if (*src_opp_id_1 == 0xf)
280 		*num_of_src_opp = 1;
281 }
282 
283 void optc2_set_dwb_source(struct timing_generator *optc,
284 		uint32_t dwb_pipe_inst)
285 {
286 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
287 
288 	if (dwb_pipe_inst == 0)
289 		REG_UPDATE(DWB_SOURCE_SELECT,
290 				OPTC_DWB0_SOURCE_SELECT, optc->inst);
291 	else if (dwb_pipe_inst == 1)
292 		REG_UPDATE(DWB_SOURCE_SELECT,
293 				OPTC_DWB1_SOURCE_SELECT, optc->inst);
294 }
295 
296 void optc2_align_vblanks(
297 	struct timing_generator *optc_master,
298 	struct timing_generator *optc_slave,
299 	uint32_t master_pixel_clock_100Hz,
300 	uint32_t slave_pixel_clock_100Hz,
301 	uint8_t master_clock_divider,
302 	uint8_t slave_clock_divider)
303 {
304 	/* accessing slave OTG registers */
305 	struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
306 
307 	uint32_t master_v_active = 0;
308 	uint32_t master_h_total = 0;
309 	uint32_t slave_h_total = 0;
310 	uint64_t L, XY;
311 	uint32_t X, Y, p = 10000;
312 	uint32_t master_update_lock;
313 
314 	/* disable slave OTG */
315 	REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
316 	/* wait until disabled */
317 	REG_WAIT(OTG_CONTROL,
318 			 OTG_CURRENT_MASTER_EN_STATE,
319 			 0, 10, 5000);
320 
321 	REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
322 
323 	/* assign slave OTG to be controlled by master update lock */
324 	REG_SET(OTG_GLOBAL_CONTROL0, 0,
325 			OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
326 
327 	/* accessing master OTG registers */
328 	optc1 = DCN10TG_FROM_TG(optc_master);
329 
330 	/* saving update lock state, not sure if it's needed */
331 	REG_GET(OTG_MASTER_UPDATE_LOCK,
332 			OTG_MASTER_UPDATE_LOCK, &master_update_lock);
333 	/* unlocking master OTG */
334 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
335 			OTG_MASTER_UPDATE_LOCK, 0);
336 
337 	REG_GET(OTG_V_BLANK_START_END,
338 			OTG_V_BLANK_START, &master_v_active);
339 	REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
340 
341 	/* calculate when to enable slave OTG */
342 	L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz;
343 	L = div_u64(L, master_h_total);
344 	L = div_u64(L, slave_pixel_clock_100Hz);
345 	XY = div_u64(L, p);
346 	Y = master_v_active - XY - 1;
347 	X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
348 
349 	/*
350 	 * set master OTG to unlock when V/H
351 	 * counters reach calculated values
352 	 */
353 	REG_UPDATE(OTG_GLOBAL_CONTROL1,
354 			   MASTER_UPDATE_LOCK_DB_EN, 1);
355 	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
356 				 MASTER_UPDATE_LOCK_DB_X,
357 				 X,
358 				 MASTER_UPDATE_LOCK_DB_Y,
359 				 Y);
360 
361 	/* lock master OTG */
362 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
363 			OTG_MASTER_UPDATE_LOCK, 1);
364 	REG_WAIT(OTG_MASTER_UPDATE_LOCK,
365 			 UPDATE_LOCK_STATUS, 1, 1, 10);
366 
367 	/* accessing slave OTG registers */
368 	optc1 = DCN10TG_FROM_TG(optc_slave);
369 
370 	/*
371 	 * enable slave OTG, the OTG is locked with
372 	 * master's update lock, so it will not run
373 	 */
374 	REG_UPDATE(OTG_CONTROL,
375 			   OTG_MASTER_EN, 1);
376 
377 	/* accessing master OTG registers */
378 	optc1 = DCN10TG_FROM_TG(optc_master);
379 
380 	/*
381 	 * unlock master OTG. When master H/V counters reach
382 	 * DB_XY point, slave OTG will start
383 	 */
384 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
385 			OTG_MASTER_UPDATE_LOCK, 0);
386 
387 	/* accessing slave OTG registers */
388 	optc1 = DCN10TG_FROM_TG(optc_slave);
389 
390 	/* wait for slave OTG to start running*/
391 	REG_WAIT(OTG_CONTROL,
392 			 OTG_CURRENT_MASTER_EN_STATE,
393 			 1, 10, 5000);
394 
395 	/* accessing master OTG registers */
396 	optc1 = DCN10TG_FROM_TG(optc_master);
397 
398 	/* disable the XY point*/
399 	REG_UPDATE(OTG_GLOBAL_CONTROL1,
400 			   MASTER_UPDATE_LOCK_DB_EN, 0);
401 	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
402 				 MASTER_UPDATE_LOCK_DB_X,
403 				 0,
404 				 MASTER_UPDATE_LOCK_DB_Y,
405 				 0);
406 
407 	/*restore master update lock*/
408 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
409 			OTG_MASTER_UPDATE_LOCK, master_update_lock);
410 
411 	/* accessing slave OTG registers */
412 	optc1 = DCN10TG_FROM_TG(optc_slave);
413 	/* restore slave to be controlled by it's own */
414 	REG_SET(OTG_GLOBAL_CONTROL0, 0,
415 			OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
416 
417 }
418 
419 void optc2_triplebuffer_lock(struct timing_generator *optc)
420 {
421 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
422 
423 	REG_SET(OTG_GLOBAL_CONTROL0, 0,
424 		OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
425 
426 	REG_SET(OTG_VUPDATE_KEEPOUT, 0,
427 		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
428 
429 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
430 		OTG_MASTER_UPDATE_LOCK, 1);
431 
432 	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
433 		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
434 				UPDATE_LOCK_STATUS, 1,
435 				1, 10);
436 }
437 
438 void optc2_triplebuffer_unlock(struct timing_generator *optc)
439 {
440 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
441 
442 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
443 		OTG_MASTER_UPDATE_LOCK, 0);
444 
445 	REG_SET(OTG_VUPDATE_KEEPOUT, 0,
446 		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
447 
448 }
449 
450 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
451 {
452 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
453 	uint32_t v_blank_start = 0;
454 	uint32_t h_blank_start = 0;
455 
456 	REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
457 
458 	REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
459 			DIG_UPDATE_LOCATION, 20);
460 
461 	REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
462 
463 	REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
464 
465 	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
466 			MASTER_UPDATE_LOCK_DB_X,
467 			(h_blank_start - 200 - 1) / optc1->opp_count,
468 			MASTER_UPDATE_LOCK_DB_Y,
469 			v_blank_start - 1);
470 }
471 
472 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
473 {
474 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
475 
476 	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
477 				MASTER_UPDATE_LOCK_DB_X,
478 				0,
479 				MASTER_UPDATE_LOCK_DB_Y,
480 				0);
481 
482 	REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
483 				DIG_UPDATE_LOCATION, 0);
484 
485 	REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
486 }
487 
488 void optc2_setup_manual_trigger(struct timing_generator *optc)
489 {
490 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
491 
492 	REG_SET_8(OTG_TRIGA_CNTL, 0,
493 			OTG_TRIGA_SOURCE_SELECT, 21,
494 			OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
495 			OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
496 			OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
497 			OTG_TRIGA_POLARITY_SELECT, 0,
498 			OTG_TRIGA_FREQUENCY_SELECT, 0,
499 			OTG_TRIGA_DELAY, 0,
500 			OTG_TRIGA_CLEAR, 1);
501 }
502 
503 void optc2_program_manual_trigger(struct timing_generator *optc)
504 {
505 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
506 
507 	REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
508 			OTG_TRIGA_MANUAL_TRIG, 1);
509 }
510 
511 bool optc2_configure_crc(struct timing_generator *optc,
512 			  const struct crc_params *params)
513 {
514 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
515 
516 	REG_SET_2(OTG_CRC_CNTL2, 0,
517 			OTG_CRC_DSC_MODE, params->dsc_mode,
518 			OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
519 
520 	return optc1_configure_crc(optc, params);
521 }
522 
523 
524 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
525 {
526 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
527 
528 	REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
529 }
530 
531 static struct timing_generator_funcs dcn20_tg_funcs = {
532 		.validate_timing = optc1_validate_timing,
533 		.program_timing = optc1_program_timing,
534 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
535 		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
536 		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
537 		.program_global_sync = optc1_program_global_sync,
538 		.enable_crtc = optc2_enable_crtc,
539 		.disable_crtc = optc1_disable_crtc,
540 		/* used by enable_timing_synchronization. Not need for FPGA */
541 		.is_counter_moving = optc1_is_counter_moving,
542 		.get_position = optc1_get_position,
543 		.get_frame_count = optc1_get_vblank_counter,
544 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
545 		.get_otg_active_size = optc1_get_otg_active_size,
546 		.set_early_control = optc1_set_early_control,
547 		/* used by enable_timing_synchronization. Not need for FPGA */
548 		.wait_for_state = optc1_wait_for_state,
549 		.set_blank = optc1_set_blank,
550 		.is_blanked = optc1_is_blanked,
551 		.set_blank_color = optc1_program_blank_color,
552 		.enable_reset_trigger = optc1_enable_reset_trigger,
553 		.enable_crtc_reset = optc1_enable_crtc_reset,
554 		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
555 		.triplebuffer_lock = optc2_triplebuffer_lock,
556 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
557 		.disable_reset_trigger = optc1_disable_reset_trigger,
558 		.lock = optc1_lock,
559 		.unlock = optc1_unlock,
560 		.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
561 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
562 		.enable_optc_clock = optc1_enable_optc_clock,
563 		.set_drr = optc1_set_drr,
564 		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
565 		.set_static_screen_control = optc1_set_static_screen_control,
566 		.program_stereo = optc1_program_stereo,
567 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
568 		.set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
569 		.tg_init = optc1_tg_init,
570 		.is_tg_enabled = optc1_is_tg_enabled,
571 		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
572 		.clear_optc_underflow = optc1_clear_optc_underflow,
573 		.setup_global_swap_lock = NULL,
574 		.get_crc = optc1_get_crc,
575 		.configure_crc = optc2_configure_crc,
576 		.set_dsc_config = optc2_set_dsc_config,
577 		.set_dwb_source = optc2_set_dwb_source,
578 		.set_odm_bypass = optc2_set_odm_bypass,
579 		.set_odm_combine = optc2_set_odm_combine,
580 		.get_optc_source = optc2_get_optc_source,
581 		.set_gsl = optc2_set_gsl,
582 		.set_gsl_source_select = optc2_set_gsl_source_select,
583 		.set_vtg_params = optc1_set_vtg_params,
584 		.program_manual_trigger = optc2_program_manual_trigger,
585 		.setup_manual_trigger = optc2_setup_manual_trigger,
586 		.get_hw_timing = optc1_get_hw_timing,
587 		.align_vblanks = optc2_align_vblanks,
588 };
589 
590 void dcn20_timing_generator_init(struct optc *optc1)
591 {
592 	optc1->base.funcs = &dcn20_tg_funcs;
593 
594 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
595 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
596 
597 	optc1->min_h_blank = 32;
598 	optc1->min_v_blank = 3;
599 	optc1->min_v_blank_interlace = 5;
600 	optc1->min_h_sync_width = 4;//	Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
601 	optc1->min_v_sync_width = 1;
602 }
603