Revision tags: v5.2.10 |
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a45804db |
| 21-Aug-2019 |
Wesley Chalmers <Wesley.Chalmers@amd.com> |
drm/amd/display: Replace for loop w/ function call [WHY] A function to adjust DPP clocks with DTO already exists; function code is identical to the code replaced here Signed
drm/amd/display: Replace for loop w/ function call [WHY] A function to adjust DPP clocks with DTO already exists; function code is identical to the code replaced here Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2 |
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37495fbd |
| 15-Jul-2019 |
Jaehyun Chung <jaehyun.chung@amd.com> |
drm/amd/display: Add work-around option to skip DCN20 clock updates [Why] Auto Overclock Memory fails for some systems that don't support p-state. [How] Implement the workaround
drm/amd/display: Add work-around option to skip DCN20 clock updates [Why] Auto Overclock Memory fails for some systems that don't support p-state. [How] Implement the workaround, and it's corresponding enable flag. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f7f38ffe |
| 15-Jul-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: fixup DPP programming sequence [why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref cloc
drm/amd/display: fixup DPP programming sequence [why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need an increased divider will temporarily have actual DPP clock drop below minimum while DTO double buffering takes effect. This results in temporary underflow. [how] To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase. When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because we do not use dividers larger than 1. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.1 |
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057fc695 |
| 08-Jul-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: support "dummy pstate" [why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that
drm/amd/display: support "dummy pstate" [why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality. Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC functionality, but not all latencies have to be supported. Existing code supports a "full p state" which allows memory clock to change, but is hard for DCN to support (as it requires very large buffers). New code will now fall back to a "dummy p state" support when "full p state" cannot be support. This easy p state support should always be allowed. [how] Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure that fallback will always work. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2, v5.1.16 |
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39bca359 |
| 02-Jul-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: add a option to force the clock at every mode change. [Description] This is for HW negative stress testing use. force reset the dispclk and dppclk even the same cloc
drm/amd/display: add a option to force the clock at every mode change. [Description] This is for HW negative stress testing use. force reset the dispclk and dppclk even the same clock already set in HW. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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925f566c |
| 27-Jun-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: add set and get clock for testing purposes add dc_set_clock add dc_get_clock this is for testing and diagnostics to get/set DPPCLK and DISPCLK. Signed-
drm/amd/display: add set and get clock for testing purposes add dc_set_clock add dc_get_clock this is for testing and diagnostics to get/set DPPCLK and DISPCLK. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1.15, v5.1.14, v5.1.13 |
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1b3c6103 |
| 21-Jun-2019 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Remove second initialization of pp_smu [why] We initialize pp_smu twice [how] Remove second initialization of pp_smu Signed-off-by: Alvin Lee <alvi
drm/amd/display: Remove second initialization of pp_smu [why] We initialize pp_smu twice [how] Remove second initialization of pp_smu Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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18b40187 |
| 21-Jun-2019 |
Su Sung Chung <Su.Chung@amd.com> |
drm/amd/display: fix not calling ppsmu to trigger PME [why] dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets filtered out by the null check [how] i
drm/amd/display: fix not calling ppsmu to trigger PME [why] dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets filtered out by the null check [how] initialize pp_smu dcn20_clk_mgr_construct Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1d0610bc |
| 20-Jun-2019 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Disable Audio on reinitialize hardware [Why] When we recover from hang, we do not want to skip the audio enable call. [How] Disable audio in dc_reinitialize
drm/amd/display: Disable Audio on reinitialize hardware [Why] When we recover from hang, we do not want to skip the audio enable call. [How] Disable audio in dc_reinitialize_hardware Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5 |
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6de20237 |
| 22-May-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: move bw calc code into helpers [Why] For better readability and reusability [How] Move snippets of BW calculation code into helpers. Signed-off-by:
drm/amd/display: move bw calc code into helpers [Why] For better readability and reusability [How] Move snippets of BW calculation code into helpers. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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93c25fbd |
| 31-May-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: initialize p_state to proper value [why] On some modes SMU will be in infinite loop state at boot, this is because driver assumes p_state_support is false, but this
drm/amd/display: initialize p_state to proper value [why] On some modes SMU will be in infinite loop state at boot, this is because driver assumes p_state_support is false, but this is the opposite of the assumed boot state by SMU. we optimize away notifying SMU about no pstate, and so they will get stuck [how] when we init clk manager, init pstate to true, so it matches driver load assumption Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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170a2398 |
| 30-May-2019 |
Su Sung Chung <Su.Chung@amd.com> |
drm/amd/display: make clk_mgr call enable_pme_wa [why] Before for raven and navi we are calling pp_smu functions for pme [how] refactor a code so we will call clk_mgr's enab
drm/amd/display: make clk_mgr call enable_pme_wa [why] Before for raven and navi we are calling pp_smu functions for pme [how] refactor a code so we will call clk_mgr's enable_pme_wa function so we can use pme_wa for future asics. This way we don't need to worry about different ASIC since clk_mgr already have that information Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7a5ab155 |
| 28-May-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: expose dentist_get_did_from_divider for future use Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.co
drm/amd/display: expose dentist_get_did_from_divider for future use Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a6465d1f |
| 28-May-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: dcn2 use fixed clocks. [Description] dcn2 use fixed clocks and not program DPP CLK or Disp_CLK. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-
drm/amd/display: dcn2 use fixed clocks. [Description] dcn2 use fixed clocks and not program DPP CLK or Disp_CLK. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6e17b5b8 |
| 27-May-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: update DCN2 uclk switch time [why] value commited to by HW team is going to be higher than pre-silicon, and will cause underflow if driver not updated [
drm/amd/display: update DCN2 uclk switch time [why] value commited to by HW team is going to be higher than pre-silicon, and will cause underflow if driver not updated [how] update hardcoded value, update pstate switching logic to fix case where with long uclk time we won't allow switch even when we should Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1.4 |
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2131f655 |
| 17-May-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: add support for forcing DCFCLK without affecting watermarks [why] useful for debugging [how] plumb a debug option in dc Signed-off-by: Jun Lei <Jun
drm/amd/display: add support for forcing DCFCLK without affecting watermarks [why] useful for debugging [how] plumb a debug option in dc Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6 |
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5940ff39 |
| 01-Apr-2019 |
Tyler DiBattista <tyler.dibattista@amd.com> |
drm/amd/display: Change Min fclk to 1.2Ghz [Why] Some nightly tests are failing since the new value for fclk is a bit too low. Also, a new test for the maximum downscale case was
drm/amd/display: Change Min fclk to 1.2Ghz [Why] Some nightly tests are failing since the new value for fclk is a bit too low. Also, a new test for the maximum downscale case was needed. [How] Updated the default value for fclk to be 1.2GHz. Signed-off-by: Tyler DiBattista <tyler.dibattista@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.0.5, v5.0.4 |
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0ff8dfe8 |
| 21-Mar-2019 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: fix fpga fclk programming We shouldnt need overhead on top of dppclk when setting fclk. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-
drm/amd/display: fix fpga fclk programming We shouldnt need overhead on top of dppclk when setting fclk. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6ba11740 |
| 16-May-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: fix pstate allow handling in dcn2 [why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support a
drm/amd/display: fix pstate allow handling in dcn2 [why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support at both min and max mpc combine rather than just min clock manager needs to update current to new pstate support before sending to pplib/smu Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c69dd2d0 |
| 08-May-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: Refactor clk_mgr functions [Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] - Pull get_active_display_cnt out to clk_mgr.
drm/amd/display: Refactor clk_mgr functions [Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] - Pull get_active_display_cnt out to clk_mgr. - Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8712bda4 |
| 09-May-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk. [Description] DMUB is using DPREF CLK, but DMCU still use displayclk. This is for updating DMCU wait_for_loop after disp
drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk. [Description] DMUB is using DPREF CLK, but DMCU still use displayclk. This is for updating DMCU wait_for_loop after display clock change. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fcee01b9 |
| 07-May-2019 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Add DCN2 clk mgr Adds support for handling of clocking relevant to the DCN2 block, including programming of the DCCG (Display Controller Clock Generator) block:
drm/amd/display: Add DCN2 clk mgr Adds support for handling of clocking relevant to the DCN2 block, including programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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