1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce100/dce_clk_mgr.h" 30 #include "reg_helper.h" 31 #include "core_types.h" 32 #include "dm_helpers.h" 33 34 #include "navi10_ip_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "clk/clk_11_0_0_offset.h" 38 #include "clk/clk_11_0_0_sh_mask.h" 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 43 44 #define REG(reg) \ 45 (clk_mgr->regs->reg) 46 47 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 48 49 #define BASE(seg) BASE_INNER(seg) 50 51 #define SR(reg_name)\ 52 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 53 mm ## reg_name 54 55 #define CLK_BASE_INNER(seg) \ 56 CLK_BASE__INST0_SEG ## seg 57 58 59 static const struct clk_mgr_registers clk_mgr_regs = { 60 CLK_REG_LIST_NV10() 61 }; 62 63 static const struct clk_mgr_shift clk_mgr_shift = { 64 CLK_MASK_SH_LIST_NV10(__SHIFT) 65 }; 66 67 static const struct clk_mgr_mask clk_mgr_mask = { 68 CLK_MASK_SH_LIST_NV10(_MASK) 69 }; 70 71 uint32_t dentist_get_did_from_divider(int divider) 72 { 73 uint32_t divider_id; 74 75 /* we want to floor here to get higher clock than required rather than lower */ 76 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 77 if (divider < DENTIST_DIVIDER_RANGE_1_START) 78 divider_id = DENTIST_BASE_DID_1; 79 else 80 divider_id = DENTIST_BASE_DID_1 81 + (divider - DENTIST_DIVIDER_RANGE_1_START) 82 / DENTIST_DIVIDER_RANGE_1_STEP; 83 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 84 divider_id = DENTIST_BASE_DID_2 85 + (divider - DENTIST_DIVIDER_RANGE_2_START) 86 / DENTIST_DIVIDER_RANGE_2_STEP; 87 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 88 divider_id = DENTIST_BASE_DID_3 89 + (divider - DENTIST_DIVIDER_RANGE_3_START) 90 / DENTIST_DIVIDER_RANGE_3_STEP; 91 } else { 92 divider_id = DENTIST_BASE_DID_4 93 + (divider - DENTIST_DIVIDER_RANGE_4_START) 94 / DENTIST_DIVIDER_RANGE_4_STEP; 95 if (divider_id > DENTIST_MAX_DID) 96 divider_id = DENTIST_MAX_DID; 97 } 98 99 return divider_id; 100 } 101 102 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 103 struct dc_state *context) 104 { 105 int i; 106 107 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 108 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 109 int dpp_inst, dppclk_khz; 110 111 if (!context->res_ctx.pipe_ctx[i].plane_state) 112 continue; 113 114 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; 115 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 116 clk_mgr->dccg->funcs->update_dpp_dto( 117 clk_mgr->dccg, dpp_inst, dppclk_khz); 118 } 119 } 120 121 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) 122 { 123 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 124 * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 125 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 126 * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 127 128 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 129 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 130 131 REG_UPDATE(DENTIST_DISPCLK_CNTL, 132 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 133 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 134 REG_UPDATE(DENTIST_DISPCLK_CNTL, 135 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 136 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 137 } 138 139 140 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 141 struct dc_state *context, 142 bool safe_to_lower) 143 { 144 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 145 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 146 struct dc *dc = clk_mgr_base->ctx->dc; 147 struct pp_smu_funcs_nv *pp_smu = NULL; 148 int display_count; 149 bool update_dppclk = false; 150 bool update_dispclk = false; 151 bool enter_display_off = false; 152 bool dpp_clock_lowered = false; 153 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 154 bool force_reset = false; 155 156 if (clk_mgr_base->clks.dispclk_khz == 0 || 157 dc->debug.force_clock_mode & 0x1) { 158 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. 159 force_reset = true; 160 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. 161 } 162 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 163 if (dc->res_pool->pp_smu) 164 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 165 166 if (display_count == 0) 167 enter_display_off = true; 168 169 if (enter_display_off == safe_to_lower) { 170 if (pp_smu && pp_smu->set_display_count) 171 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 172 } 173 174 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 175 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 176 if (pp_smu && pp_smu->set_voltage_by_freq) 177 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 178 } 179 180 if (dc->debug.force_min_dcfclk_mhz > 0) 181 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 182 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 183 184 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 185 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 186 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 187 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 188 } 189 190 if (should_set_clock(safe_to_lower, 191 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 192 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 193 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 194 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 195 } 196 197 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 198 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 199 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 200 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 201 } 202 203 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 204 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 205 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 206 if (pp_smu && pp_smu->set_pstate_handshake_support) 207 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 208 } 209 210 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 211 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 212 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 213 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 214 } 215 216 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 217 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 218 dpp_clock_lowered = true; 219 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 220 221 if (pp_smu && pp_smu->set_voltage_by_freq) 222 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 223 224 update_dppclk = true; 225 } 226 227 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 228 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 229 if (pp_smu && pp_smu->set_voltage_by_freq) 230 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 231 232 update_dispclk = true; 233 } 234 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 235 if (dpp_clock_lowered) { 236 // if clock is being lowered, increase DTO before lowering refclk 237 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 238 dcn20_update_clocks_update_dentist(clk_mgr); 239 } else { 240 // if clock is being raised, increase refclk before lowering DTO 241 if (update_dppclk || update_dispclk) 242 dcn20_update_clocks_update_dentist(clk_mgr); 243 if (update_dppclk) 244 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 245 } 246 } 247 if (update_dispclk && 248 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 249 /*update dmcu for wait_loop count*/ 250 dmcu->funcs->set_psr_wait_loop(dmcu, 251 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 252 } 253 } 254 255 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 256 struct dc_state *context, 257 bool safe_to_lower) 258 { 259 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 260 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 261 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 262 263 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 264 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 265 } 266 267 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 268 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 269 } 270 271 if (should_set_clock(safe_to_lower, 272 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 273 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 274 } 275 276 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 277 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 278 } 279 280 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 281 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 282 } 283 284 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 285 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 286 } 287 288 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 289 clk_mgr->clks.fclk_khz = fclk_adj; 290 } 291 292 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 293 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 294 } 295 296 /* Both fclk and dppclk ref are run on the same scemi clock so we 297 * need to keep the same value for both 298 */ 299 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 300 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 301 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 302 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 303 304 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 305 } 306 307 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 308 { 309 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 310 // Assumption is that boot state always supports pstate 311 clk_mgr->clks.p_state_change_support = true; 312 clk_mgr->clks.prev_p_state_change_support = true; 313 } 314 315 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 316 { 317 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 318 struct pp_smu_funcs_nv *pp_smu = NULL; 319 320 if (clk_mgr->pp_smu) { 321 pp_smu = &clk_mgr->pp_smu->nv_funcs; 322 323 if (pp_smu->set_pme_wa_enable) 324 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 325 } 326 } 327 328 void dcn2_get_clock(struct clk_mgr *clk_mgr, 329 struct dc_state *context, 330 enum dc_clock_type clock_type, 331 struct dc_clock_config *clock_cfg) 332 { 333 334 if (clock_type == DC_CLOCK_TYPE_DISPCLK) { 335 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; 336 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; 337 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; 338 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; 339 } 340 if (clock_type == DC_CLOCK_TYPE_DPPCLK) { 341 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 342 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; 343 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; 344 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; 345 } 346 } 347 348 static struct clk_mgr_funcs dcn2_funcs = { 349 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 350 .update_clocks = dcn2_update_clocks, 351 .init_clocks = dcn2_init_clocks, 352 .enable_pme_wa = dcn2_enable_pme_wa, 353 .get_clock = dcn2_get_clock, 354 }; 355 356 357 void dcn20_clk_mgr_construct( 358 struct dc_context *ctx, 359 struct clk_mgr_internal *clk_mgr, 360 struct pp_smu_funcs *pp_smu, 361 struct dccg *dccg) 362 { 363 clk_mgr->base.ctx = ctx; 364 clk_mgr->pp_smu = pp_smu; 365 clk_mgr->base.funcs = &dcn2_funcs; 366 clk_mgr->regs = &clk_mgr_regs; 367 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 368 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 369 370 clk_mgr->dccg = dccg; 371 clk_mgr->dfs_bypass_disp_clk = 0; 372 373 clk_mgr->dprefclk_ss_percentage = 0; 374 clk_mgr->dprefclk_ss_divider = 1000; 375 clk_mgr->ss_on_dprefclk = false; 376 377 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 378 379 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 380 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 381 clk_mgr->dentist_vco_freq_khz = 3850000; 382 383 } else { 384 /* DFS Slice 2 should be used for DPREFCLK */ 385 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 386 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 387 int target_div = dentist_get_divider_from_did(dprefclk_did); 388 389 /* get FbMult value */ 390 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 391 struct fixed31_32 pll_req; 392 393 /* set up a fixed-point number 394 * this works because the int part is on the right edge of the register 395 * and the frac part is on the left edge 396 */ 397 398 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 399 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 400 401 /* multiply by REFCLK period */ 402 pll_req = dc_fixpt_mul_int(pll_req, 100000); 403 404 /* integer part is now VCO frequency in kHz */ 405 clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 406 407 /* in case we don't get a value from the register, use default */ 408 if (clk_mgr->dentist_vco_freq_khz == 0) 409 clk_mgr->dentist_vco_freq_khz = 3850000; 410 411 /* Calculate the DPREFCLK in kHz.*/ 412 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 413 * clk_mgr->dentist_vco_freq_khz) / target_div; 414 } 415 //Integrated_info table does not exist on dGPU projects so should not be referenced 416 //anywhere in code for dGPUs. 417 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 418 clk_mgr->dfs_bypass_enabled = false; 419 420 dce_clock_read_ss_info(clk_mgr); 421 } 422 423