1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce100/dce_clk_mgr.h" 30 #include "reg_helper.h" 31 #include "core_types.h" 32 #include "dm_helpers.h" 33 34 #include "navi10_ip_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "clk/clk_11_0_0_offset.h" 38 #include "clk/clk_11_0_0_sh_mask.h" 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 43 44 #define REG(reg) \ 45 (clk_mgr->regs->reg) 46 47 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 48 49 #define BASE(seg) BASE_INNER(seg) 50 51 #define SR(reg_name)\ 52 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 53 mm ## reg_name 54 55 #define CLK_BASE_INNER(seg) \ 56 CLK_BASE__INST0_SEG ## seg 57 58 59 static const struct clk_mgr_registers clk_mgr_regs = { 60 CLK_REG_LIST_NV10() 61 }; 62 63 static const struct clk_mgr_shift clk_mgr_shift = { 64 CLK_MASK_SH_LIST_NV10(__SHIFT) 65 }; 66 67 static const struct clk_mgr_mask clk_mgr_mask = { 68 CLK_MASK_SH_LIST_NV10(_MASK) 69 }; 70 71 uint32_t dentist_get_did_from_divider(int divider) 72 { 73 uint32_t divider_id; 74 75 /* we want to floor here to get higher clock than required rather than lower */ 76 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 77 if (divider < DENTIST_DIVIDER_RANGE_1_START) 78 divider_id = DENTIST_BASE_DID_1; 79 else 80 divider_id = DENTIST_BASE_DID_1 81 + (divider - DENTIST_DIVIDER_RANGE_1_START) 82 / DENTIST_DIVIDER_RANGE_1_STEP; 83 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 84 divider_id = DENTIST_BASE_DID_2 85 + (divider - DENTIST_DIVIDER_RANGE_2_START) 86 / DENTIST_DIVIDER_RANGE_2_STEP; 87 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 88 divider_id = DENTIST_BASE_DID_3 89 + (divider - DENTIST_DIVIDER_RANGE_3_START) 90 / DENTIST_DIVIDER_RANGE_3_STEP; 91 } else { 92 divider_id = DENTIST_BASE_DID_4 93 + (divider - DENTIST_DIVIDER_RANGE_4_START) 94 / DENTIST_DIVIDER_RANGE_4_STEP; 95 if (divider_id > DENTIST_MAX_DID) 96 divider_id = DENTIST_MAX_DID; 97 } 98 99 return divider_id; 100 } 101 102 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 103 struct dc_state *context) 104 { 105 int i; 106 107 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 108 int dpp_inst, dppclk_khz; 109 110 if (!context->res_ctx.pipe_ctx[i].plane_state) 111 continue; 112 113 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; 114 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 115 clk_mgr->dccg->funcs->update_dpp_dto( 116 clk_mgr->dccg, dpp_inst, dppclk_khz, false); 117 } 118 } 119 120 static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) 121 { 122 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 123 * clk_mgr->dentist_vco_freq_khz / khz; 124 125 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 126 127 REG_UPDATE(DENTIST_DISPCLK_CNTL, 128 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 129 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 130 } 131 132 static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) 133 { 134 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 135 * clk_mgr->dentist_vco_freq_khz / khz; 136 137 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 138 139 REG_UPDATE(DENTIST_DISPCLK_CNTL, 140 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 141 } 142 143 static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) 144 { 145 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 146 struct dc *dc = clk_mgr_base->ctx->dc; 147 struct pp_smu_funcs_nv *pp_smu = NULL; 148 bool going_up = clk_mgr->base.clks.dispclk_khz < khz; 149 150 if (dc->res_pool->pp_smu) 151 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 152 153 clk_mgr->base.clks.dispclk_khz = khz; 154 155 if (going_up && pp_smu && pp_smu->set_voltage_by_freq) 156 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 157 158 update_display_clk(clk_mgr, khz); 159 160 if (!going_up && pp_smu && pp_smu->set_voltage_by_freq) 161 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 162 } 163 164 static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) 165 { 166 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 167 struct dc *dc = clk_mgr_base->ctx->dc; 168 struct pp_smu_funcs_nv *pp_smu = NULL; 169 bool going_up = clk_mgr->base.clks.dppclk_khz < khz; 170 171 if (dc->res_pool->pp_smu) 172 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 173 174 clk_mgr->base.clks.dppclk_khz = khz; 175 clk_mgr->dccg->ref_dppclk = khz; 176 177 if (going_up && pp_smu && pp_smu->set_voltage_by_freq) 178 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 179 180 update_global_dpp_clk(clk_mgr, khz); 181 182 if (!going_up && pp_smu && pp_smu->set_voltage_by_freq) 183 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 184 } 185 186 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 187 struct dc_state *context, 188 bool safe_to_lower) 189 { 190 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 191 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 192 struct dc *dc = clk_mgr_base->ctx->dc; 193 struct pp_smu_funcs_nv *pp_smu = NULL; 194 int display_count; 195 bool update_dispclk = false; 196 bool enter_display_off = false; 197 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 198 bool force_reset = false; 199 200 if (dc->work_arounds.skip_clock_update) 201 return; 202 203 if (clk_mgr_base->clks.dispclk_khz == 0 || 204 dc->debug.force_clock_mode & 0x1) { 205 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. 206 force_reset = true; 207 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. 208 } 209 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 210 if (dc->res_pool->pp_smu) 211 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 212 213 if (display_count == 0) 214 enter_display_off = true; 215 216 if (enter_display_off == safe_to_lower) { 217 if (pp_smu && pp_smu->set_display_count) 218 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 219 } 220 221 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 222 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 223 if (pp_smu && pp_smu->set_voltage_by_freq) 224 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 225 } 226 227 228 if (dc->debug.force_min_dcfclk_mhz > 0) 229 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 230 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 231 232 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 233 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 234 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 235 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 236 } 237 238 if (should_set_clock(safe_to_lower, 239 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 240 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 241 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 242 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 243 } 244 245 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 246 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 247 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 248 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 249 } 250 251 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 252 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 253 254 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 255 if (pp_smu && pp_smu->set_pstate_handshake_support) 256 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 257 } 258 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 259 260 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 261 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 262 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 263 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 264 } 265 266 if (dc->config.forced_clocks == false) { 267 // First update display clock 268 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) 269 request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz); 270 271 // Updating DPP clock requires some more logic 272 if (!safe_to_lower) { 273 // For pre-programming, we need to make sure any DPP clock that will go up has to go up 274 275 // First raise the global reference if needed 276 if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz) 277 request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz); 278 279 // Then raise any dividers that need raising 280 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 281 } else { 282 // For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs 283 284 if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz) 285 request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz); 286 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 287 288 } 289 } 290 if (update_dispclk && 291 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 292 /*update dmcu for wait_loop count*/ 293 dmcu->funcs->set_psr_wait_loop(dmcu, 294 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 295 } 296 } 297 298 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 299 struct dc_state *context, 300 bool safe_to_lower) 301 { 302 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 303 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 304 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 305 306 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 307 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 308 } 309 310 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 311 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 312 } 313 314 if (should_set_clock(safe_to_lower, 315 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 316 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 317 } 318 319 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 320 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 321 } 322 323 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 324 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 325 } 326 327 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 328 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 329 } 330 331 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 332 clk_mgr->clks.fclk_khz = fclk_adj; 333 } 334 335 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 336 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 337 } 338 339 /* Both fclk and dppclk ref are run on the same scemi clock so we 340 * need to keep the same value for both 341 */ 342 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 343 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 344 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 345 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 346 347 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 348 } 349 350 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 351 { 352 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 353 // Assumption is that boot state always supports pstate 354 clk_mgr->clks.p_state_change_support = true; 355 clk_mgr->clks.prev_p_state_change_support = true; 356 } 357 358 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 359 { 360 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 361 struct pp_smu_funcs_nv *pp_smu = NULL; 362 363 if (clk_mgr->pp_smu) { 364 pp_smu = &clk_mgr->pp_smu->nv_funcs; 365 366 if (pp_smu->set_pme_wa_enable) 367 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 368 } 369 } 370 371 void dcn2_get_clock(struct clk_mgr *clk_mgr, 372 struct dc_state *context, 373 enum dc_clock_type clock_type, 374 struct dc_clock_config *clock_cfg) 375 { 376 377 if (clock_type == DC_CLOCK_TYPE_DISPCLK) { 378 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; 379 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; 380 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; 381 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; 382 } 383 if (clock_type == DC_CLOCK_TYPE_DPPCLK) { 384 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 385 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; 386 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; 387 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; 388 } 389 } 390 391 static struct clk_mgr_funcs dcn2_funcs = { 392 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 393 .update_clocks = dcn2_update_clocks, 394 .init_clocks = dcn2_init_clocks, 395 .enable_pme_wa = dcn2_enable_pme_wa, 396 .get_clock = dcn2_get_clock, 397 }; 398 399 400 void dcn20_clk_mgr_construct( 401 struct dc_context *ctx, 402 struct clk_mgr_internal *clk_mgr, 403 struct pp_smu_funcs *pp_smu, 404 struct dccg *dccg) 405 { 406 clk_mgr->base.ctx = ctx; 407 clk_mgr->pp_smu = pp_smu; 408 clk_mgr->base.funcs = &dcn2_funcs; 409 clk_mgr->regs = &clk_mgr_regs; 410 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 411 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 412 413 clk_mgr->dccg = dccg; 414 clk_mgr->dfs_bypass_disp_clk = 0; 415 416 clk_mgr->dprefclk_ss_percentage = 0; 417 clk_mgr->dprefclk_ss_divider = 1000; 418 clk_mgr->ss_on_dprefclk = false; 419 420 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 421 422 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 423 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 424 clk_mgr->dentist_vco_freq_khz = 3850000; 425 426 } else { 427 /* DFS Slice 2 should be used for DPREFCLK */ 428 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 429 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 430 int target_div = dentist_get_divider_from_did(dprefclk_did); 431 432 /* get FbMult value */ 433 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 434 struct fixed31_32 pll_req; 435 436 /* set up a fixed-point number 437 * this works because the int part is on the right edge of the register 438 * and the frac part is on the left edge 439 */ 440 441 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 442 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 443 444 /* multiply by REFCLK period */ 445 pll_req = dc_fixpt_mul_int(pll_req, 100000); 446 447 /* integer part is now VCO frequency in kHz */ 448 clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 449 450 /* in case we don't get a value from the register, use default */ 451 if (clk_mgr->dentist_vco_freq_khz == 0) 452 clk_mgr->dentist_vco_freq_khz = 3850000; 453 454 /* Calculate the DPREFCLK in kHz.*/ 455 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 456 * clk_mgr->dentist_vco_freq_khz) / target_div; 457 } 458 //Integrated_info table does not exist on dGPU projects so should not be referenced 459 //anywhere in code for dGPUs. 460 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 461 clk_mgr->dfs_bypass_enabled = false; 462 463 dce_clock_read_ss_info(clk_mgr); 464 } 465 466