1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "dce100/dce_clk_mgr.h" 32 #include "reg_helper.h" 33 #include "core_types.h" 34 #include "dm_helpers.h" 35 36 #include "navi10_ip_offset.h" 37 #include "dcn/dcn_2_0_0_offset.h" 38 #include "dcn/dcn_2_0_0_sh_mask.h" 39 #include "clk/clk_11_0_0_offset.h" 40 #include "clk/clk_11_0_0_sh_mask.h" 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 45 46 #define REG(reg) \ 47 (clk_mgr->regs->reg) 48 49 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 50 51 #define BASE(seg) BASE_INNER(seg) 52 53 #define SR(reg_name)\ 54 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 55 mm ## reg_name 56 57 #define CLK_BASE_INNER(seg) \ 58 CLK_BASE__INST0_SEG ## seg 59 60 61 static const struct clk_mgr_registers clk_mgr_regs = { 62 CLK_REG_LIST_NV10() 63 }; 64 65 static const struct clk_mgr_shift clk_mgr_shift = { 66 CLK_MASK_SH_LIST_NV10(__SHIFT) 67 }; 68 69 static const struct clk_mgr_mask clk_mgr_mask = { 70 CLK_MASK_SH_LIST_NV10(_MASK) 71 }; 72 73 static uint32_t dentist_get_did_from_divider(int divider) 74 { 75 uint32_t divider_id; 76 77 /* we want to floor here to get higher clock than required rather than lower */ 78 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 79 if (divider < DENTIST_DIVIDER_RANGE_1_START) 80 divider_id = DENTIST_BASE_DID_1; 81 else 82 divider_id = DENTIST_BASE_DID_1 83 + (divider - DENTIST_DIVIDER_RANGE_1_START) 84 / DENTIST_DIVIDER_RANGE_1_STEP; 85 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 86 divider_id = DENTIST_BASE_DID_2 87 + (divider - DENTIST_DIVIDER_RANGE_2_START) 88 / DENTIST_DIVIDER_RANGE_2_STEP; 89 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 90 divider_id = DENTIST_BASE_DID_3 91 + (divider - DENTIST_DIVIDER_RANGE_3_START) 92 / DENTIST_DIVIDER_RANGE_3_STEP; 93 } else { 94 divider_id = DENTIST_BASE_DID_4 95 + (divider - DENTIST_DIVIDER_RANGE_4_START) 96 / DENTIST_DIVIDER_RANGE_4_STEP; 97 if (divider_id > DENTIST_MAX_DID) 98 divider_id = DENTIST_MAX_DID; 99 } 100 101 return divider_id; 102 } 103 104 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 105 struct dc_state *context) 106 { 107 int i; 108 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 111 int dpp_inst, dppclk_khz; 112 113 if (!context->res_ctx.pipe_ctx[i].plane_state) 114 continue; 115 116 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; 117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 118 clk_mgr->dccg->funcs->update_dpp_dto( 119 clk_mgr->dccg, dpp_inst, dppclk_khz); 120 } 121 } 122 123 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) 124 { 125 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 126 * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 127 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 128 * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 129 130 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 131 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 132 133 REG_UPDATE(DENTIST_DISPCLK_CNTL, 134 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 135 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 136 REG_UPDATE(DENTIST_DISPCLK_CNTL, 137 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 138 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 139 } 140 141 142 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 143 struct dc_state *context, 144 bool safe_to_lower) 145 { 146 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 147 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 148 struct dc *dc = clk_mgr_base->ctx->dc; 149 struct pp_smu_funcs_nv *pp_smu = NULL; 150 int display_count; 151 bool update_dppclk = false; 152 bool update_dispclk = false; 153 bool enter_display_off = false; 154 bool dpp_clock_lowered = false; 155 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 156 157 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 158 if (dc->res_pool->pp_smu) 159 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 160 161 if (display_count == 0) 162 enter_display_off = true; 163 164 if (enter_display_off == safe_to_lower) { 165 if (pp_smu && pp_smu->set_display_count) 166 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 167 } 168 169 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 170 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 171 if (pp_smu && pp_smu->set_voltage_by_freq) 172 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 173 } 174 175 if (dc->debug.force_min_dcfclk_mhz > 0) 176 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 177 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 178 179 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 180 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 181 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 182 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 183 } 184 185 if (should_set_clock(safe_to_lower, 186 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 187 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 188 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 189 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 190 } 191 192 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 193 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 194 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 195 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 196 } 197 198 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 199 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 200 if (pp_smu && pp_smu->set_pstate_handshake_support) 201 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 202 } 203 204 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 205 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 206 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 207 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 208 } 209 210 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 211 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 212 dpp_clock_lowered = true; 213 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 214 215 if (pp_smu && pp_smu->set_voltage_by_freq) 216 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 217 218 update_dppclk = true; 219 } 220 221 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 222 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 223 if (pp_smu && pp_smu->set_voltage_by_freq) 224 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 225 226 update_dispclk = true; 227 } 228 if (dc->config.forced_clocks == false) { 229 if (dpp_clock_lowered) { 230 // if clock is being lowered, increase DTO before lowering refclk 231 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 232 dcn20_update_clocks_update_dentist(clk_mgr); 233 } else { 234 // if clock is being raised, increase refclk before lowering DTO 235 if (update_dppclk || update_dispclk) 236 dcn20_update_clocks_update_dentist(clk_mgr); 237 if (update_dppclk) 238 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 239 } 240 } 241 if (update_dispclk && 242 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 243 /*update dmcu for wait_loop count*/ 244 dmcu->funcs->set_psr_wait_loop(dmcu, 245 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 246 } 247 } 248 249 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 250 struct dc_state *context, 251 bool safe_to_lower) 252 { 253 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 254 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 255 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 256 257 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 258 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 259 } 260 261 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 262 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 263 } 264 265 if (should_set_clock(safe_to_lower, 266 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 267 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 268 } 269 270 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 271 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 272 } 273 274 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 275 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 276 } 277 278 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 279 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 280 } 281 282 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 283 clk_mgr->clks.fclk_khz = fclk_adj; 284 } 285 286 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 287 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 288 } 289 290 /* Both fclk and dppclk ref are run on the same scemi clock so we 291 * need to keep the same value for both 292 */ 293 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 294 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 295 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 296 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 297 298 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 299 } 300 301 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 302 { 303 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 304 } 305 306 static struct clk_mgr_funcs dcn2_funcs = { 307 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 308 .update_clocks = dcn2_update_clocks, 309 .init_clocks = dcn2_init_clocks 310 }; 311 312 313 void dcn20_clk_mgr_construct( 314 struct dc_context *ctx, 315 struct clk_mgr_internal *clk_mgr, 316 struct pp_smu_funcs *pp_smu, 317 struct dccg *dccg) 318 { 319 clk_mgr->base.ctx = ctx; 320 clk_mgr->base.funcs = &dcn2_funcs; 321 clk_mgr->regs = &clk_mgr_regs; 322 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 323 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 324 325 clk_mgr->dccg = dccg; 326 clk_mgr->dfs_bypass_disp_clk = 0; 327 328 clk_mgr->dprefclk_ss_percentage = 0; 329 clk_mgr->dprefclk_ss_divider = 1000; 330 clk_mgr->ss_on_dprefclk = false; 331 332 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 333 334 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 335 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 336 clk_mgr->dentist_vco_freq_khz = 3850000; 337 338 } else { 339 /* DFS Slice 2 should be used for DPREFCLK */ 340 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 341 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 342 int target_div = dentist_get_divider_from_did(dprefclk_did); 343 344 /* get FbMult value */ 345 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 346 struct fixed31_32 pll_req; 347 348 /* set up a fixed-point number 349 * this works because the int part is on the right edge of the register 350 * and the frac part is on the left edge 351 */ 352 353 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 354 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 355 356 /* multiply by REFCLK period */ 357 pll_req = dc_fixpt_mul_int(pll_req, 100000); 358 359 /* integer part is now VCO frequency in kHz */ 360 clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 361 362 /* in case we don't get a value from the register, use default */ 363 if (clk_mgr->dentist_vco_freq_khz == 0) 364 clk_mgr->dentist_vco_freq_khz = 3850000; 365 366 /* Calculate the DPREFCLK in kHz.*/ 367 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 368 * clk_mgr->dentist_vco_freq_khz) / target_div; 369 } 370 //Integrated_info table does not exist on dGPU projects so should not be referenced 371 //anywhere in code for dGPUs. 372 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 373 clk_mgr->dfs_bypass_enabled = false; 374 375 dce_clock_read_ss_info(clk_mgr); 376 } 377 378