#
8bc7b360 |
| 19-Mar-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: split mmhub callbacks into ras and non-ras ones
mmhub ras is only avaiable in cerntain mmhub ip generation.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <
drm/amdgpu: split mmhub callbacks into ras and non-ras ones
mmhub ras is only avaiable in cerntain mmhub ip generation.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
49070c4e |
| 17-Mar-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: split umc callbacks to ras and non-ras ones
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver on
drm/amdgpu: split umc callbacks to ras and non-ras ones
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver only initializes umc ras callbacks when it manages umc ras.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
52137ca8 |
| 18-Mar-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: move xgmi ras functions to xgmi_ras_funcs
xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver onl
drm/amdgpu: move xgmi ras functions to xgmi_ras_funcs
xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver only initializes xgmi ras functions when it manages xgmi ras.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9fd5543e |
| 08-Mar-2021 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: allow variable BO struct creation
Allow allocating BO structures with different structure size than struct amdgpu_bo.
v2: Check bo_ptr_size in all amdgpu_bo_create() caller.
Signed-off
drm/amdgpu: allow variable BO struct creation
Allow allocating BO structures with different structure size than struct amdgpu_bo.
v2: Check bo_ptr_size in all amdgpu_bo_create() caller.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b7f1e04 |
| 24-Mar-2021 |
Philip Cox <Philip.Cox@amd.com> |
drm/amdgpu: Set amdgpu.noretry=1 for Arcturus
Setting amdgpu.noretry=1 as default for Arcturus.
Signed-off-by: Philip Cox <Philip.Cox@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signe
drm/amdgpu: Set amdgpu.noretry=1 for Arcturus
Setting amdgpu.noretry=1 as default for Arcturus.
Signed-off-by: Philip Cox <Philip.Cox@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
63dbb0db |
| 11-Feb-2021 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Make noretry the default on Aldebaran
This is needed for best machine learning performance. XNACK can still be enabled per-process if needed.
Signed-off-by: Felix Kuehling <Felix.Kuehli
drm/amdgpu: Make noretry the default on Aldebaran
This is needed for best machine learning performance. XNACK can still be enabled per-process if needed.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Tested-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
79194dac |
| 22-Jan-2021 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Fix GART page table s-bit
For the new 2-level GART table, the last PDE0 points to PTB. Since PTB is in vram and right now we are runing under s=0 mode (vram is treated as FB carveout), s
drm/amdgpu: Fix GART page table s-bit
For the new 2-level GART table, the last PDE0 points to PTB. Since PTB is in vram and right now we are runing under s=0 mode (vram is treated as FB carveout), so the s bit of this PDE0 should be set to 0.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
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#
a2902c09 |
| 17-Sep-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Add function to allocate and fill PDB0
Add functions to allocate PDB0, map it for CPU access, and fill it.
Those functions are only used for 2-level vmid0 page table construction
Signe
drm/amdgpu: Add function to allocate and fill PDB0
Add functions to allocate PDB0, map it for CPU access, and fill it.
Those functions are only used for 2-level vmid0 page table construction
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.10 |
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#
f527f310 |
| 15-Sep-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Placement of gart and vram in sysvm aperture
If use GART for FB translation, place both vram and gart to sysvm aperture. AGP aperture is not set up in this case because it is not used
S
drm/amdgpu: Placement of gart and vram in sysvm aperture
If use GART for FB translation, place both vram and gart to sysvm aperture. AGP aperture is not set up in this case because it is not used
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f1dc12ca |
| 02-Oct-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Moved gart_size calculation to mc_init functions
In amdgpu_gmc_gart_location function, gart_size is adjusted by a smu_prv_buffer_size. This logic shouldn't belong to this function. Move
drm/amdgpu: Moved gart_size calculation to mc_init functions
In amdgpu_gmc_gart_location function, gart_size is adjusted by a smu_prv_buffer_size. This logic shouldn't belong to this function. Move the logic to the mc_init functions
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
58aa7790 |
| 26-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: enable TMZ by default on Raven asics
This has been stable for a while.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e11bfb99 |
| 09-Dec-2020 |
Christian König <christian.koenig@amd.com> |
drm/ttm: cleanup BO size handling v3
Based on an idea from Dave, but cleaned up a bit.
We had multiple fields for essentially the same thing.
Now bo->base.size is the original size of the BO in ar
drm/ttm: cleanup BO size handling v3
Based on an idea from Dave, but cleaned up a bit.
We had multiple fields for essentially the same thing.
Now bo->base.size is the original size of the BO in arbitrary units, usually bytes.
bo->mem.num_pages is the size in number of pages in the resource domain of bo->mem.mem_type.
v2: use the GEM object size instead of the BO size v3: fix printks in some places
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> (v1) Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/406831/
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#
088fb29b |
| 16-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix vbios reservation handling on SR-IOV
There is no reserveration so set the size to 0. Fixes a regression on SR-IOV.
Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Ale
drm/amdgpu: fix vbios reservation handling on SR-IOV
There is no reserveration so set the size to 0. Fixes a regression on SR-IOV.
Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7eded018 |
| 14-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix regression in vbios reservation handling on headless
We need to move the check under the non-headless case, otherwise we always reserve the VGA save size.
Fixes: 157fe68d74c2ad ("dr
drm/amdgpu: fix regression in vbios reservation handling on headless
We need to move the check under the non-headless case, otherwise we always reserve the VGA save size.
Fixes: 157fe68d74c2ad ("drm/amdgpu: fix size calculation with stolen vga memory") Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
30018679 |
| 07-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix size calculation with stolen vga memory
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size.
Acked-by: Christian König <christian.koenig
drm/amdgpu: fix size calculation with stolen vga memory
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7624897c |
| 30-Nov-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: default noretry=0 for navi1x and newer (v2)
There are no performance advantages to setting it to 1 and it causes stability issues in some cases.
v2: simplify the code
Bug: https://gitl
drm/amdgpu: default noretry=0 for navi1x and newer (v2)
There are no performance advantages to setting it to 1 and it causes stability issues in some cases.
v2: simplify the code
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1374 Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9ccde05c |
| 23-Nov-2020 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdgpu: set default value of noretry to 1 for specified asic
noretry = 0 casue KFDGraphicsInterop test failed on SRIOV platform for vega10, so set noretry to 1 for vega10.
Signed-off-by: Stanle
drm/amdgpu: set default value of noretry to 1 for specified asic
noretry = 0 casue KFDGraphicsInterop test failed on SRIOV platform for vega10, so set noretry to 1 for vega10.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ff08711c |
| 13-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/amdgpu/amdgpu_gmc: Demote one and fix another function header
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:69: warning: Function parameter or me
drm/amd/amdgpu/amdgpu_gmc: Demote one and fix another function header
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:69: warning: Function parameter or member 'bo' not described in 'amdgpu_gmc_pd_addr' drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:121: warning: Function parameter or member 'bo' not described in 'amdgpu_gmc_agp_addr' drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:121: warning: Excess function parameter 'tbo' description in 'amdgpu_gmc_agp_addr'
Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9d6f27f9 |
| 29-Oct-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: allow TMZ on vangogh
Uses the same pathes as navi.
Reviewed-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deu
drm/amdgpu: allow TMZ on vangogh
Uses the same pathes as navi.
Reviewed-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e34b8fee |
| 21-Oct-2020 |
Christian König <christian.koenig@amd.com> |
drm/ttm: merge ttm_dma_tt back into ttm_tt
It makes no difference to kmalloc if the structure is 48 or 64 bytes in size.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Dave
drm/ttm: merge ttm_dma_tt back into ttm_tt
It makes no difference to kmalloc if the structure is 48 or 64 bytes in size.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/396950/
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#
1ed685df |
| 19-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: enable noretry for Sienna_Cichlid/Navy_Flounder/Dimgrey_Cavefish
set noretry default value to 1 for sienna_cichlid/navy_founder/dimgrey_cavefish.
Signed-off-by: Chengming Gui <Jack.
drm/amd/amdgpu: enable noretry for Sienna_Cichlid/Navy_Flounder/Dimgrey_Cavefish
set noretry default value to 1 for sienna_cichlid/navy_founder/dimgrey_cavefish.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
92aeeafb |
| 12-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: set the default value of noretry to 1 for some dGPUs
noretry = 0 cause some dGPU's kfd page fault tests fail, so set noretry to 1 for these special ASICs: vega20/navi10/navi14
v2: m
drm/amd/amdgpu: set the default value of noretry to 1 for some dGPUs
noretry = 0 cause some dGPU's kfd page fault tests fail, so set noretry to 1 for these special ASICs: vega20/navi10/navi14
v2: merge raven and default case due to the same setting v3: remove ARCTURUS
Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Acked-by: Felix Kuhling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b4ea4c5 |
| 30-Sep-2020 |
Christian König <christian.koenig@amd.com> |
drm/ttm: set the tt caching state at creation time
All drivers can determine the tt caching state at creation time, no need to do this on the fly during every validation.
Signed-off-by: Christian K
drm/ttm: set the tt caching state at creation time
All drivers can determine the tt caching state at creation time, no need to do this on the fly during every validation.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Link: https://patchwork.freedesktop.org/patch/394253/
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#
c51e3679 |
| 14-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix regression in vbios reservation handling on headless
[ Upstream commit 7eded018bfeccb365963bb51be731a9f99aeea59 ]
We need to move the check under the non-headless case, otherwise we
drm/amdgpu: fix regression in vbios reservation handling on headless
[ Upstream commit 7eded018bfeccb365963bb51be731a9f99aeea59 ]
We need to move the check under the non-headless case, otherwise we always reserve the VGA save size.
Fixes: 157fe68d74c2ad ("drm/amdgpu: fix size calculation with stolen vga memory") Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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#
157fe68d |
| 07-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix size calculation with stolen vga memory
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size.
Acked-by: Christian König <christian.koenig
drm/amdgpu: fix size calculation with stolen vga memory
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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