1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_gmc.h" 31 #include "amdgpu_ras.h" 32 #include "amdgpu_xgmi.h" 33 34 /** 35 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 36 * 37 * @adev: amdgpu_device pointer 38 * 39 * Allocate video memory for pdb0 and map it for CPU access 40 * Returns 0 for success, error for failure. 41 */ 42 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 43 { 44 int r; 45 struct amdgpu_bo_param bp; 46 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 47 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 48 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 49 50 memset(&bp, 0, sizeof(bp)); 51 bp.size = PAGE_ALIGN((npdes + 1) * 8); 52 bp.byte_align = PAGE_SIZE; 53 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 54 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 55 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 56 bp.type = ttm_bo_type_kernel; 57 bp.resv = NULL; 58 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 59 if (r) 60 return r; 61 62 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 63 if (unlikely(r != 0)) 64 goto bo_reserve_failure; 65 66 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 67 if (r) 68 goto bo_pin_failure; 69 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 70 if (r) 71 goto bo_kmap_failure; 72 73 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 74 return 0; 75 76 bo_kmap_failure: 77 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 78 bo_pin_failure: 79 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 80 bo_reserve_failure: 81 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 82 return r; 83 } 84 85 /** 86 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 87 * 88 * @bo: the BO to get the PDE for 89 * @level: the level in the PD hirarchy 90 * @addr: resulting addr 91 * @flags: resulting flags 92 * 93 * Get the address and flags to be used for a PDE (Page Directory Entry). 94 */ 95 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 96 uint64_t *addr, uint64_t *flags) 97 { 98 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 99 100 switch (bo->tbo.mem.mem_type) { 101 case TTM_PL_TT: 102 *addr = bo->tbo.ttm->dma_address[0]; 103 break; 104 case TTM_PL_VRAM: 105 *addr = amdgpu_bo_gpu_offset(bo); 106 break; 107 default: 108 *addr = 0; 109 break; 110 } 111 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem); 112 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 113 } 114 115 /* 116 * amdgpu_gmc_pd_addr - return the address of the root directory 117 */ 118 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 119 { 120 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 121 uint64_t pd_addr; 122 123 /* TODO: move that into ASIC specific code */ 124 if (adev->asic_type >= CHIP_VEGA10) { 125 uint64_t flags = AMDGPU_PTE_VALID; 126 127 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 128 pd_addr |= flags; 129 } else { 130 pd_addr = amdgpu_bo_gpu_offset(bo); 131 } 132 return pd_addr; 133 } 134 135 /** 136 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 137 * 138 * @adev: amdgpu_device pointer 139 * @cpu_pt_addr: cpu address of the page table 140 * @gpu_page_idx: entry in the page table to update 141 * @addr: dst addr to write into pte/pde 142 * @flags: access flags 143 * 144 * Update the page tables using CPU. 145 */ 146 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 147 uint32_t gpu_page_idx, uint64_t addr, 148 uint64_t flags) 149 { 150 void __iomem *ptr = (void *)cpu_pt_addr; 151 uint64_t value; 152 153 /* 154 * The following is for PTE only. GART does not have PDEs. 155 */ 156 value = addr & 0x0000FFFFFFFFF000ULL; 157 value |= flags; 158 writeq(value, ptr + (gpu_page_idx * 8)); 159 return 0; 160 } 161 162 /** 163 * amdgpu_gmc_agp_addr - return the address in the AGP address space 164 * 165 * @bo: TTM BO which needs the address, must be in GTT domain 166 * 167 * Tries to figure out how to access the BO through the AGP aperture. Returns 168 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 169 */ 170 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 171 { 172 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 173 174 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 175 return AMDGPU_BO_INVALID_OFFSET; 176 177 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 178 return AMDGPU_BO_INVALID_OFFSET; 179 180 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 181 } 182 183 /** 184 * amdgpu_gmc_vram_location - try to find VRAM location 185 * 186 * @adev: amdgpu device structure holding all necessary information 187 * @mc: memory controller structure holding memory information 188 * @base: base address at which to put VRAM 189 * 190 * Function will try to place VRAM at base address provided 191 * as parameter. 192 */ 193 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 194 u64 base) 195 { 196 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 197 198 mc->vram_start = base; 199 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 200 if (limit && limit < mc->real_vram_size) 201 mc->real_vram_size = limit; 202 203 if (mc->xgmi.num_physical_nodes == 0) { 204 mc->fb_start = mc->vram_start; 205 mc->fb_end = mc->vram_end; 206 } 207 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 208 mc->mc_vram_size >> 20, mc->vram_start, 209 mc->vram_end, mc->real_vram_size >> 20); 210 } 211 212 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 213 * 214 * @adev: amdgpu device structure holding all necessary information 215 * @mc: memory controller structure holding memory information 216 * 217 * This function is only used if use GART for FB translation. In such 218 * case, we use sysvm aperture (vmid0 page tables) for both vram 219 * and gart (aka system memory) access. 220 * 221 * GPUVM (and our organization of vmid0 page tables) require sysvm 222 * aperture to be placed at a location aligned with 8 times of native 223 * page size. For example, if vm_context0_cntl.page_table_block_size 224 * is 12, then native page size is 8G (2M*2^12), sysvm should start 225 * with a 64G aligned address. For simplicity, we just put sysvm at 226 * address 0. So vram start at address 0 and gart is right after vram. 227 */ 228 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 229 { 230 u64 hive_vram_start = 0; 231 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 232 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 233 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 234 mc->gart_start = hive_vram_end + 1; 235 mc->gart_end = mc->gart_start + mc->gart_size - 1; 236 mc->fb_start = hive_vram_start; 237 mc->fb_end = hive_vram_end; 238 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 239 mc->mc_vram_size >> 20, mc->vram_start, 240 mc->vram_end, mc->real_vram_size >> 20); 241 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 242 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 243 } 244 245 /** 246 * amdgpu_gmc_gart_location - try to find GART location 247 * 248 * @adev: amdgpu device structure holding all necessary information 249 * @mc: memory controller structure holding memory information 250 * 251 * Function will place try to place GART before or after VRAM. 252 * If GART size is bigger than space left then we ajust GART size. 253 * Thus function will never fails. 254 */ 255 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 256 { 257 const uint64_t four_gb = 0x100000000ULL; 258 u64 size_af, size_bf; 259 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 260 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 261 262 /* VCE doesn't like it when BOs cross a 4GB segment, so align 263 * the GART base on a 4GB boundary as well. 264 */ 265 size_bf = mc->fb_start; 266 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 267 268 if (mc->gart_size > max(size_bf, size_af)) { 269 dev_warn(adev->dev, "limiting GART\n"); 270 mc->gart_size = max(size_bf, size_af); 271 } 272 273 if ((size_bf >= mc->gart_size && size_bf < size_af) || 274 (size_af < mc->gart_size)) 275 mc->gart_start = 0; 276 else 277 mc->gart_start = max_mc_address - mc->gart_size + 1; 278 279 mc->gart_start &= ~(four_gb - 1); 280 mc->gart_end = mc->gart_start + mc->gart_size - 1; 281 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 282 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 283 } 284 285 /** 286 * amdgpu_gmc_agp_location - try to find AGP location 287 * @adev: amdgpu device structure holding all necessary information 288 * @mc: memory controller structure holding memory information 289 * 290 * Function will place try to find a place for the AGP BAR in the MC address 291 * space. 292 * 293 * AGP BAR will be assigned the largest available hole in the address space. 294 * Should be called after VRAM and GART locations are setup. 295 */ 296 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 297 { 298 const uint64_t sixteen_gb = 1ULL << 34; 299 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 300 u64 size_af, size_bf; 301 302 if (amdgpu_sriov_vf(adev)) { 303 mc->agp_start = 0xffffffffffff; 304 mc->agp_end = 0x0; 305 mc->agp_size = 0; 306 307 return; 308 } 309 310 if (mc->fb_start > mc->gart_start) { 311 size_bf = (mc->fb_start & sixteen_gb_mask) - 312 ALIGN(mc->gart_end + 1, sixteen_gb); 313 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 314 } else { 315 size_bf = mc->fb_start & sixteen_gb_mask; 316 size_af = (mc->gart_start & sixteen_gb_mask) - 317 ALIGN(mc->fb_end + 1, sixteen_gb); 318 } 319 320 if (size_bf > size_af) { 321 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 322 mc->agp_size = size_bf; 323 } else { 324 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 325 mc->agp_size = size_af; 326 } 327 328 mc->agp_end = mc->agp_start + mc->agp_size - 1; 329 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 330 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 331 } 332 333 /** 334 * amdgpu_gmc_filter_faults - filter VM faults 335 * 336 * @adev: amdgpu device structure 337 * @addr: address of the VM fault 338 * @pasid: PASID of the process causing the fault 339 * @timestamp: timestamp of the fault 340 * 341 * Returns: 342 * True if the fault was filtered and should not be processed further. 343 * False if the fault is a new one and needs to be handled. 344 */ 345 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 346 uint16_t pasid, uint64_t timestamp) 347 { 348 struct amdgpu_gmc *gmc = &adev->gmc; 349 350 uint64_t stamp, key = addr << 4 | pasid; 351 struct amdgpu_gmc_fault *fault; 352 uint32_t hash; 353 354 /* If we don't have space left in the ring buffer return immediately */ 355 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 356 AMDGPU_GMC_FAULT_TIMEOUT; 357 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 358 return true; 359 360 /* Try to find the fault in the hash */ 361 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 362 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 363 while (fault->timestamp >= stamp) { 364 uint64_t tmp; 365 366 if (fault->key == key) 367 return true; 368 369 tmp = fault->timestamp; 370 fault = &gmc->fault_ring[fault->next]; 371 372 /* Check if the entry was reused */ 373 if (fault->timestamp >= tmp) 374 break; 375 } 376 377 /* Add the fault to the ring */ 378 fault = &gmc->fault_ring[gmc->last_fault]; 379 fault->key = key; 380 fault->timestamp = timestamp; 381 382 /* And update the hash */ 383 fault->next = gmc->fault_hash[hash].idx; 384 gmc->fault_hash[hash].idx = gmc->last_fault++; 385 return false; 386 } 387 388 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 389 { 390 int r; 391 392 if (adev->umc.funcs && adev->umc.funcs->ras_late_init) { 393 r = adev->umc.funcs->ras_late_init(adev); 394 if (r) 395 return r; 396 } 397 398 if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) { 399 r = adev->mmhub.funcs->ras_late_init(adev); 400 if (r) 401 return r; 402 } 403 404 return amdgpu_xgmi_ras_late_init(adev); 405 } 406 407 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 408 { 409 amdgpu_umc_ras_fini(adev); 410 amdgpu_mmhub_ras_fini(adev); 411 amdgpu_xgmi_ras_fini(adev); 412 } 413 414 /* 415 * The latest engine allocation on gfx9/10 is: 416 * Engine 2, 3: firmware 417 * Engine 0, 1, 4~16: amdgpu ring, 418 * subject to change when ring number changes 419 * Engine 17: Gart flushes 420 */ 421 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 422 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 423 424 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 425 { 426 struct amdgpu_ring *ring; 427 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 428 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 429 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 430 unsigned i; 431 unsigned vmhub, inv_eng; 432 433 for (i = 0; i < adev->num_rings; ++i) { 434 ring = adev->rings[i]; 435 vmhub = ring->funcs->vmhub; 436 437 if (ring == &adev->mes.ring) 438 continue; 439 440 inv_eng = ffs(vm_inv_engs[vmhub]); 441 if (!inv_eng) { 442 dev_err(adev->dev, "no VM inv eng for ring %s\n", 443 ring->name); 444 return -EINVAL; 445 } 446 447 ring->vm_inv_eng = inv_eng - 1; 448 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 449 450 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 451 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 452 } 453 454 return 0; 455 } 456 457 /** 458 * amdgpu_tmz_set -- check and set if a device supports TMZ 459 * @adev: amdgpu_device pointer 460 * 461 * Check and set if an the device @adev supports Trusted Memory 462 * Zones (TMZ). 463 */ 464 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 465 { 466 switch (adev->asic_type) { 467 case CHIP_RAVEN: 468 if (amdgpu_tmz == 0) { 469 adev->gmc.tmz_enabled = false; 470 dev_info(adev->dev, 471 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 472 } else { 473 adev->gmc.tmz_enabled = true; 474 dev_info(adev->dev, 475 "Trusted Memory Zone (TMZ) feature enabled\n"); 476 } 477 break; 478 case CHIP_RENOIR: 479 case CHIP_NAVI10: 480 case CHIP_NAVI14: 481 case CHIP_NAVI12: 482 case CHIP_VANGOGH: 483 /* Don't enable it by default yet. 484 */ 485 if (amdgpu_tmz < 1) { 486 adev->gmc.tmz_enabled = false; 487 dev_info(adev->dev, 488 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 489 } else { 490 adev->gmc.tmz_enabled = true; 491 dev_info(adev->dev, 492 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 493 } 494 break; 495 default: 496 adev->gmc.tmz_enabled = false; 497 dev_warn(adev->dev, 498 "Trusted Memory Zone (TMZ) feature not supported\n"); 499 break; 500 } 501 } 502 503 /** 504 * amdgpu_noretry_set -- set per asic noretry defaults 505 * @adev: amdgpu_device pointer 506 * 507 * Set a per asic default for the no-retry parameter. 508 * 509 */ 510 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 511 { 512 struct amdgpu_gmc *gmc = &adev->gmc; 513 514 switch (adev->asic_type) { 515 case CHIP_VEGA10: 516 case CHIP_VEGA20: 517 /* 518 * noretry = 0 will cause kfd page fault tests fail 519 * for some ASICs, so set default to 1 for these ASICs. 520 */ 521 if (amdgpu_noretry == -1) 522 gmc->noretry = 1; 523 else 524 gmc->noretry = amdgpu_noretry; 525 break; 526 case CHIP_RAVEN: 527 default: 528 /* Raven currently has issues with noretry 529 * regardless of what we decide for other 530 * asics, we should leave raven with 531 * noretry = 0 until we root cause the 532 * issues. 533 * 534 * default this to 0 for now, but we may want 535 * to change this in the future for certain 536 * GPUs as it can increase performance in 537 * certain cases. 538 */ 539 if (amdgpu_noretry == -1) 540 gmc->noretry = 0; 541 else 542 gmc->noretry = amdgpu_noretry; 543 break; 544 } 545 } 546 547 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 548 bool enable) 549 { 550 struct amdgpu_vmhub *hub; 551 u32 tmp, reg, i; 552 553 hub = &adev->vmhub[hub_type]; 554 for (i = 0; i < 16; i++) { 555 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 556 557 tmp = RREG32(reg); 558 if (enable) 559 tmp |= hub->vm_cntx_cntl_vm_fault; 560 else 561 tmp &= ~hub->vm_cntx_cntl_vm_fault; 562 563 WREG32(reg, tmp); 564 } 565 } 566 567 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 568 { 569 unsigned size; 570 571 /* 572 * TODO: 573 * Currently there is a bug where some memory client outside 574 * of the driver writes to first 8M of VRAM on S3 resume, 575 * this overrides GART which by default gets placed in first 8M and 576 * causes VM_FAULTS once GTT is accessed. 577 * Keep the stolen memory reservation until the while this is not solved. 578 */ 579 switch (adev->asic_type) { 580 case CHIP_VEGA10: 581 case CHIP_RAVEN: 582 case CHIP_RENOIR: 583 adev->mman.keep_stolen_vga_memory = true; 584 break; 585 default: 586 adev->mman.keep_stolen_vga_memory = false; 587 break; 588 } 589 590 if (amdgpu_sriov_vf(adev) || 591 !amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) { 592 size = 0; 593 } else { 594 size = amdgpu_gmc_get_vbios_fb_size(adev); 595 596 if (adev->mman.keep_stolen_vga_memory) 597 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 598 } 599 600 /* set to 0 if the pre-OS buffer uses up most of vram */ 601 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 602 size = 0; 603 604 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 605 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 606 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 607 } else { 608 adev->mman.stolen_vga_size = size; 609 adev->mman.stolen_extended_size = 0; 610 } 611 } 612 613 /** 614 * amdgpu_gmc_init_pdb0 - initialize PDB0 615 * 616 * @adev: amdgpu_device pointer 617 * 618 * This function is only used when GART page table is used 619 * for FB address translatioin. In such a case, we construct 620 * a 2-level system VM page table: PDB0->PTB, to cover both 621 * VRAM of the hive and system memory. 622 * 623 * PDB0 is static, initialized once on driver initialization. 624 * The first n entries of PDB0 are used as PTE by setting 625 * P bit to 1, pointing to VRAM. The n+1'th entry points 626 * to a big PTB covering system memory. 627 * 628 */ 629 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 630 { 631 int i; 632 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 633 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 634 */ 635 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 636 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 637 u64 vram_addr = adev->vm_manager.vram_base_offset - 638 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 639 u64 vram_end = vram_addr + vram_size; 640 u64 gart_ptb_gpu_pa = amdgpu_bo_gpu_offset(adev->gart.bo) + 641 adev->vm_manager.vram_base_offset - adev->gmc.vram_start; 642 643 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 644 flags |= AMDGPU_PTE_WRITEABLE; 645 flags |= AMDGPU_PTE_SNOOPED; 646 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 647 flags |= AMDGPU_PDE_PTE; 648 649 /* The first n PDE0 entries are used as PTE, 650 * pointing to vram 651 */ 652 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 653 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 654 655 /* The n+1'th PDE0 entry points to a huge 656 * PTB who has more than 512 entries each 657 * pointing to a 4K system page 658 */ 659 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM; 660 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 661 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 662 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 663 } 664