1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_gmc.h" 31 #include "amdgpu_ras.h" 32 #include "amdgpu_xgmi.h" 33 34 /** 35 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 36 * 37 * @bo: the BO to get the PDE for 38 * @level: the level in the PD hirarchy 39 * @addr: resulting addr 40 * @flags: resulting flags 41 * 42 * Get the address and flags to be used for a PDE (Page Directory Entry). 43 */ 44 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 45 uint64_t *addr, uint64_t *flags) 46 { 47 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 48 49 switch (bo->tbo.mem.mem_type) { 50 case TTM_PL_TT: 51 *addr = bo->tbo.ttm->dma_address[0]; 52 break; 53 case TTM_PL_VRAM: 54 *addr = amdgpu_bo_gpu_offset(bo); 55 break; 56 default: 57 *addr = 0; 58 break; 59 } 60 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem); 61 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 62 } 63 64 /* 65 * amdgpu_gmc_pd_addr - return the address of the root directory 66 */ 67 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 68 { 69 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 70 uint64_t pd_addr; 71 72 /* TODO: move that into ASIC specific code */ 73 if (adev->asic_type >= CHIP_VEGA10) { 74 uint64_t flags = AMDGPU_PTE_VALID; 75 76 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 77 pd_addr |= flags; 78 } else { 79 pd_addr = amdgpu_bo_gpu_offset(bo); 80 } 81 return pd_addr; 82 } 83 84 /** 85 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 86 * 87 * @adev: amdgpu_device pointer 88 * @cpu_pt_addr: cpu address of the page table 89 * @gpu_page_idx: entry in the page table to update 90 * @addr: dst addr to write into pte/pde 91 * @flags: access flags 92 * 93 * Update the page tables using CPU. 94 */ 95 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 96 uint32_t gpu_page_idx, uint64_t addr, 97 uint64_t flags) 98 { 99 void __iomem *ptr = (void *)cpu_pt_addr; 100 uint64_t value; 101 102 /* 103 * The following is for PTE only. GART does not have PDEs. 104 */ 105 value = addr & 0x0000FFFFFFFFF000ULL; 106 value |= flags; 107 writeq(value, ptr + (gpu_page_idx * 8)); 108 return 0; 109 } 110 111 /** 112 * amdgpu_gmc_agp_addr - return the address in the AGP address space 113 * 114 * @bo: TTM BO which needs the address, must be in GTT domain 115 * 116 * Tries to figure out how to access the BO through the AGP aperture. Returns 117 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 118 */ 119 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 120 { 121 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 122 123 if (bo->num_pages != 1 || bo->ttm->caching == ttm_cached) 124 return AMDGPU_BO_INVALID_OFFSET; 125 126 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 127 return AMDGPU_BO_INVALID_OFFSET; 128 129 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 130 } 131 132 /** 133 * amdgpu_gmc_vram_location - try to find VRAM location 134 * 135 * @adev: amdgpu device structure holding all necessary information 136 * @mc: memory controller structure holding memory information 137 * @base: base address at which to put VRAM 138 * 139 * Function will try to place VRAM at base address provided 140 * as parameter. 141 */ 142 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 143 u64 base) 144 { 145 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 146 147 mc->vram_start = base; 148 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 149 if (limit && limit < mc->real_vram_size) 150 mc->real_vram_size = limit; 151 152 if (mc->xgmi.num_physical_nodes == 0) { 153 mc->fb_start = mc->vram_start; 154 mc->fb_end = mc->vram_end; 155 } 156 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 157 mc->mc_vram_size >> 20, mc->vram_start, 158 mc->vram_end, mc->real_vram_size >> 20); 159 } 160 161 /** 162 * amdgpu_gmc_gart_location - try to find GART location 163 * 164 * @adev: amdgpu device structure holding all necessary information 165 * @mc: memory controller structure holding memory information 166 * 167 * Function will place try to place GART before or after VRAM. 168 * 169 * If GART size is bigger than space left then we ajust GART size. 170 * Thus function will never fails. 171 */ 172 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 173 { 174 const uint64_t four_gb = 0x100000000ULL; 175 u64 size_af, size_bf; 176 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 177 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 178 179 mc->gart_size += adev->pm.smu_prv_buffer_size; 180 181 /* VCE doesn't like it when BOs cross a 4GB segment, so align 182 * the GART base on a 4GB boundary as well. 183 */ 184 size_bf = mc->fb_start; 185 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 186 187 if (mc->gart_size > max(size_bf, size_af)) { 188 dev_warn(adev->dev, "limiting GART\n"); 189 mc->gart_size = max(size_bf, size_af); 190 } 191 192 if ((size_bf >= mc->gart_size && size_bf < size_af) || 193 (size_af < mc->gart_size)) 194 mc->gart_start = 0; 195 else 196 mc->gart_start = max_mc_address - mc->gart_size + 1; 197 198 mc->gart_start &= ~(four_gb - 1); 199 mc->gart_end = mc->gart_start + mc->gart_size - 1; 200 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 201 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 202 } 203 204 /** 205 * amdgpu_gmc_agp_location - try to find AGP location 206 * @adev: amdgpu device structure holding all necessary information 207 * @mc: memory controller structure holding memory information 208 * 209 * Function will place try to find a place for the AGP BAR in the MC address 210 * space. 211 * 212 * AGP BAR will be assigned the largest available hole in the address space. 213 * Should be called after VRAM and GART locations are setup. 214 */ 215 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 216 { 217 const uint64_t sixteen_gb = 1ULL << 34; 218 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 219 u64 size_af, size_bf; 220 221 if (amdgpu_sriov_vf(adev)) { 222 mc->agp_start = 0xffffffffffff; 223 mc->agp_end = 0x0; 224 mc->agp_size = 0; 225 226 return; 227 } 228 229 if (mc->fb_start > mc->gart_start) { 230 size_bf = (mc->fb_start & sixteen_gb_mask) - 231 ALIGN(mc->gart_end + 1, sixteen_gb); 232 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 233 } else { 234 size_bf = mc->fb_start & sixteen_gb_mask; 235 size_af = (mc->gart_start & sixteen_gb_mask) - 236 ALIGN(mc->fb_end + 1, sixteen_gb); 237 } 238 239 if (size_bf > size_af) { 240 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 241 mc->agp_size = size_bf; 242 } else { 243 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 244 mc->agp_size = size_af; 245 } 246 247 mc->agp_end = mc->agp_start + mc->agp_size - 1; 248 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 249 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 250 } 251 252 /** 253 * amdgpu_gmc_filter_faults - filter VM faults 254 * 255 * @adev: amdgpu device structure 256 * @addr: address of the VM fault 257 * @pasid: PASID of the process causing the fault 258 * @timestamp: timestamp of the fault 259 * 260 * Returns: 261 * True if the fault was filtered and should not be processed further. 262 * False if the fault is a new one and needs to be handled. 263 */ 264 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 265 uint16_t pasid, uint64_t timestamp) 266 { 267 struct amdgpu_gmc *gmc = &adev->gmc; 268 269 uint64_t stamp, key = addr << 4 | pasid; 270 struct amdgpu_gmc_fault *fault; 271 uint32_t hash; 272 273 /* If we don't have space left in the ring buffer return immediately */ 274 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 275 AMDGPU_GMC_FAULT_TIMEOUT; 276 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 277 return true; 278 279 /* Try to find the fault in the hash */ 280 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 281 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 282 while (fault->timestamp >= stamp) { 283 uint64_t tmp; 284 285 if (fault->key == key) 286 return true; 287 288 tmp = fault->timestamp; 289 fault = &gmc->fault_ring[fault->next]; 290 291 /* Check if the entry was reused */ 292 if (fault->timestamp >= tmp) 293 break; 294 } 295 296 /* Add the fault to the ring */ 297 fault = &gmc->fault_ring[gmc->last_fault]; 298 fault->key = key; 299 fault->timestamp = timestamp; 300 301 /* And update the hash */ 302 fault->next = gmc->fault_hash[hash].idx; 303 gmc->fault_hash[hash].idx = gmc->last_fault++; 304 return false; 305 } 306 307 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 308 { 309 int r; 310 311 if (adev->umc.funcs && adev->umc.funcs->ras_late_init) { 312 r = adev->umc.funcs->ras_late_init(adev); 313 if (r) 314 return r; 315 } 316 317 if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) { 318 r = adev->mmhub.funcs->ras_late_init(adev); 319 if (r) 320 return r; 321 } 322 323 return amdgpu_xgmi_ras_late_init(adev); 324 } 325 326 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 327 { 328 amdgpu_umc_ras_fini(adev); 329 amdgpu_mmhub_ras_fini(adev); 330 amdgpu_xgmi_ras_fini(adev); 331 } 332 333 /* 334 * The latest engine allocation on gfx9/10 is: 335 * Engine 2, 3: firmware 336 * Engine 0, 1, 4~16: amdgpu ring, 337 * subject to change when ring number changes 338 * Engine 17: Gart flushes 339 */ 340 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 341 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 342 343 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 344 { 345 struct amdgpu_ring *ring; 346 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 347 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 348 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 349 unsigned i; 350 unsigned vmhub, inv_eng; 351 352 for (i = 0; i < adev->num_rings; ++i) { 353 ring = adev->rings[i]; 354 vmhub = ring->funcs->vmhub; 355 356 if (ring == &adev->mes.ring) 357 continue; 358 359 inv_eng = ffs(vm_inv_engs[vmhub]); 360 if (!inv_eng) { 361 dev_err(adev->dev, "no VM inv eng for ring %s\n", 362 ring->name); 363 return -EINVAL; 364 } 365 366 ring->vm_inv_eng = inv_eng - 1; 367 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 368 369 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 370 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 371 } 372 373 return 0; 374 } 375 376 /** 377 * amdgpu_tmz_set -- check and set if a device supports TMZ 378 * @adev: amdgpu_device pointer 379 * 380 * Check and set if an the device @adev supports Trusted Memory 381 * Zones (TMZ). 382 */ 383 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 384 { 385 switch (adev->asic_type) { 386 case CHIP_RAVEN: 387 case CHIP_RENOIR: 388 case CHIP_NAVI10: 389 case CHIP_NAVI14: 390 case CHIP_NAVI12: 391 case CHIP_VANGOGH: 392 /* Don't enable it by default yet. 393 */ 394 if (amdgpu_tmz < 1) { 395 adev->gmc.tmz_enabled = false; 396 dev_info(adev->dev, 397 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 398 } else { 399 adev->gmc.tmz_enabled = true; 400 dev_info(adev->dev, 401 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 402 } 403 break; 404 default: 405 adev->gmc.tmz_enabled = false; 406 dev_warn(adev->dev, 407 "Trusted Memory Zone (TMZ) feature not supported\n"); 408 break; 409 } 410 } 411 412 /** 413 * amdgpu_noretry_set -- set per asic noretry defaults 414 * @adev: amdgpu_device pointer 415 * 416 * Set a per asic default for the no-retry parameter. 417 * 418 */ 419 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 420 { 421 struct amdgpu_gmc *gmc = &adev->gmc; 422 423 switch (adev->asic_type) { 424 case CHIP_VEGA20: 425 case CHIP_NAVI10: 426 case CHIP_NAVI14: 427 case CHIP_SIENNA_CICHLID: 428 case CHIP_NAVY_FLOUNDER: 429 case CHIP_DIMGREY_CAVEFISH: 430 /* 431 * noretry = 0 will cause kfd page fault tests fail 432 * for some ASICs, so set default to 1 for these ASICs. 433 */ 434 if (amdgpu_noretry == -1) 435 gmc->noretry = 1; 436 else 437 gmc->noretry = amdgpu_noretry; 438 break; 439 case CHIP_RAVEN: 440 default: 441 /* Raven currently has issues with noretry 442 * regardless of what we decide for other 443 * asics, we should leave raven with 444 * noretry = 0 until we root cause the 445 * issues. 446 * 447 * default this to 0 for now, but we may want 448 * to change this in the future for certain 449 * GPUs as it can increase performance in 450 * certain cases. 451 */ 452 if (amdgpu_noretry == -1) 453 gmc->noretry = 0; 454 else 455 gmc->noretry = amdgpu_noretry; 456 break; 457 } 458 } 459 460 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 461 bool enable) 462 { 463 struct amdgpu_vmhub *hub; 464 u32 tmp, reg, i; 465 466 hub = &adev->vmhub[hub_type]; 467 for (i = 0; i < 16; i++) { 468 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 469 470 tmp = RREG32(reg); 471 if (enable) 472 tmp |= hub->vm_cntx_cntl_vm_fault; 473 else 474 tmp &= ~hub->vm_cntx_cntl_vm_fault; 475 476 WREG32(reg, tmp); 477 } 478 } 479 480 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 481 { 482 unsigned size; 483 484 /* 485 * TODO: 486 * Currently there is a bug where some memory client outside 487 * of the driver writes to first 8M of VRAM on S3 resume, 488 * this overrides GART which by default gets placed in first 8M and 489 * causes VM_FAULTS once GTT is accessed. 490 * Keep the stolen memory reservation until the while this is not solved. 491 */ 492 switch (adev->asic_type) { 493 case CHIP_VEGA10: 494 case CHIP_RAVEN: 495 case CHIP_RENOIR: 496 adev->mman.keep_stolen_vga_memory = true; 497 break; 498 default: 499 adev->mman.keep_stolen_vga_memory = false; 500 break; 501 } 502 503 if (!amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) 504 size = 0; 505 else 506 size = amdgpu_gmc_get_vbios_fb_size(adev); 507 508 /* set to 0 if the pre-OS buffer uses up most of vram */ 509 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 510 size = 0; 511 512 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 513 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 514 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 515 } else { 516 adev->mman.stolen_vga_size = size; 517 adev->mman.stolen_extended_size = 0; 518 } 519 } 520