1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_gmc.h" 31 #include "amdgpu_ras.h" 32 #include "amdgpu_xgmi.h" 33 34 /** 35 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 36 * 37 * @adev: amdgpu_device pointer 38 * 39 * Allocate video memory for pdb0 and map it for CPU access 40 * Returns 0 for success, error for failure. 41 */ 42 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 43 { 44 int r; 45 struct amdgpu_bo_param bp; 46 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 47 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 48 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 49 50 memset(&bp, 0, sizeof(bp)); 51 bp.size = PAGE_ALIGN((npdes + 1) * 8); 52 bp.byte_align = PAGE_SIZE; 53 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 54 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 55 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 56 bp.type = ttm_bo_type_kernel; 57 bp.resv = NULL; 58 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 59 60 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 61 if (r) 62 return r; 63 64 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 65 if (unlikely(r != 0)) 66 goto bo_reserve_failure; 67 68 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 69 if (r) 70 goto bo_pin_failure; 71 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 72 if (r) 73 goto bo_kmap_failure; 74 75 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 76 return 0; 77 78 bo_kmap_failure: 79 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 80 bo_pin_failure: 81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 82 bo_reserve_failure: 83 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 84 return r; 85 } 86 87 /** 88 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 89 * 90 * @bo: the BO to get the PDE for 91 * @level: the level in the PD hirarchy 92 * @addr: resulting addr 93 * @flags: resulting flags 94 * 95 * Get the address and flags to be used for a PDE (Page Directory Entry). 96 */ 97 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 98 uint64_t *addr, uint64_t *flags) 99 { 100 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 101 102 switch (bo->tbo.mem.mem_type) { 103 case TTM_PL_TT: 104 *addr = bo->tbo.ttm->dma_address[0]; 105 break; 106 case TTM_PL_VRAM: 107 *addr = amdgpu_bo_gpu_offset(bo); 108 break; 109 default: 110 *addr = 0; 111 break; 112 } 113 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem); 114 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 115 } 116 117 /* 118 * amdgpu_gmc_pd_addr - return the address of the root directory 119 */ 120 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 121 { 122 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 123 uint64_t pd_addr; 124 125 /* TODO: move that into ASIC specific code */ 126 if (adev->asic_type >= CHIP_VEGA10) { 127 uint64_t flags = AMDGPU_PTE_VALID; 128 129 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 130 pd_addr |= flags; 131 } else { 132 pd_addr = amdgpu_bo_gpu_offset(bo); 133 } 134 return pd_addr; 135 } 136 137 /** 138 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 139 * 140 * @adev: amdgpu_device pointer 141 * @cpu_pt_addr: cpu address of the page table 142 * @gpu_page_idx: entry in the page table to update 143 * @addr: dst addr to write into pte/pde 144 * @flags: access flags 145 * 146 * Update the page tables using CPU. 147 */ 148 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 149 uint32_t gpu_page_idx, uint64_t addr, 150 uint64_t flags) 151 { 152 void __iomem *ptr = (void *)cpu_pt_addr; 153 uint64_t value; 154 155 /* 156 * The following is for PTE only. GART does not have PDEs. 157 */ 158 value = addr & 0x0000FFFFFFFFF000ULL; 159 value |= flags; 160 writeq(value, ptr + (gpu_page_idx * 8)); 161 return 0; 162 } 163 164 /** 165 * amdgpu_gmc_agp_addr - return the address in the AGP address space 166 * 167 * @bo: TTM BO which needs the address, must be in GTT domain 168 * 169 * Tries to figure out how to access the BO through the AGP aperture. Returns 170 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 171 */ 172 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 173 { 174 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 175 176 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 177 return AMDGPU_BO_INVALID_OFFSET; 178 179 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 180 return AMDGPU_BO_INVALID_OFFSET; 181 182 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 183 } 184 185 /** 186 * amdgpu_gmc_vram_location - try to find VRAM location 187 * 188 * @adev: amdgpu device structure holding all necessary information 189 * @mc: memory controller structure holding memory information 190 * @base: base address at which to put VRAM 191 * 192 * Function will try to place VRAM at base address provided 193 * as parameter. 194 */ 195 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 196 u64 base) 197 { 198 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 199 200 mc->vram_start = base; 201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 202 if (limit && limit < mc->real_vram_size) 203 mc->real_vram_size = limit; 204 205 if (mc->xgmi.num_physical_nodes == 0) { 206 mc->fb_start = mc->vram_start; 207 mc->fb_end = mc->vram_end; 208 } 209 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 210 mc->mc_vram_size >> 20, mc->vram_start, 211 mc->vram_end, mc->real_vram_size >> 20); 212 } 213 214 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 215 * 216 * @adev: amdgpu device structure holding all necessary information 217 * @mc: memory controller structure holding memory information 218 * 219 * This function is only used if use GART for FB translation. In such 220 * case, we use sysvm aperture (vmid0 page tables) for both vram 221 * and gart (aka system memory) access. 222 * 223 * GPUVM (and our organization of vmid0 page tables) require sysvm 224 * aperture to be placed at a location aligned with 8 times of native 225 * page size. For example, if vm_context0_cntl.page_table_block_size 226 * is 12, then native page size is 8G (2M*2^12), sysvm should start 227 * with a 64G aligned address. For simplicity, we just put sysvm at 228 * address 0. So vram start at address 0 and gart is right after vram. 229 */ 230 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 231 { 232 u64 hive_vram_start = 0; 233 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 234 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 235 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 236 mc->gart_start = hive_vram_end + 1; 237 mc->gart_end = mc->gart_start + mc->gart_size - 1; 238 mc->fb_start = hive_vram_start; 239 mc->fb_end = hive_vram_end; 240 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 241 mc->mc_vram_size >> 20, mc->vram_start, 242 mc->vram_end, mc->real_vram_size >> 20); 243 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 244 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 245 } 246 247 /** 248 * amdgpu_gmc_gart_location - try to find GART location 249 * 250 * @adev: amdgpu device structure holding all necessary information 251 * @mc: memory controller structure holding memory information 252 * 253 * Function will place try to place GART before or after VRAM. 254 * If GART size is bigger than space left then we ajust GART size. 255 * Thus function will never fails. 256 */ 257 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 258 { 259 const uint64_t four_gb = 0x100000000ULL; 260 u64 size_af, size_bf; 261 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 262 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 263 264 /* VCE doesn't like it when BOs cross a 4GB segment, so align 265 * the GART base on a 4GB boundary as well. 266 */ 267 size_bf = mc->fb_start; 268 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 269 270 if (mc->gart_size > max(size_bf, size_af)) { 271 dev_warn(adev->dev, "limiting GART\n"); 272 mc->gart_size = max(size_bf, size_af); 273 } 274 275 if ((size_bf >= mc->gart_size && size_bf < size_af) || 276 (size_af < mc->gart_size)) 277 mc->gart_start = 0; 278 else 279 mc->gart_start = max_mc_address - mc->gart_size + 1; 280 281 mc->gart_start &= ~(four_gb - 1); 282 mc->gart_end = mc->gart_start + mc->gart_size - 1; 283 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 284 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 285 } 286 287 /** 288 * amdgpu_gmc_agp_location - try to find AGP location 289 * @adev: amdgpu device structure holding all necessary information 290 * @mc: memory controller structure holding memory information 291 * 292 * Function will place try to find a place for the AGP BAR in the MC address 293 * space. 294 * 295 * AGP BAR will be assigned the largest available hole in the address space. 296 * Should be called after VRAM and GART locations are setup. 297 */ 298 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 299 { 300 const uint64_t sixteen_gb = 1ULL << 34; 301 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 302 u64 size_af, size_bf; 303 304 if (amdgpu_sriov_vf(adev)) { 305 mc->agp_start = 0xffffffffffff; 306 mc->agp_end = 0x0; 307 mc->agp_size = 0; 308 309 return; 310 } 311 312 if (mc->fb_start > mc->gart_start) { 313 size_bf = (mc->fb_start & sixteen_gb_mask) - 314 ALIGN(mc->gart_end + 1, sixteen_gb); 315 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 316 } else { 317 size_bf = mc->fb_start & sixteen_gb_mask; 318 size_af = (mc->gart_start & sixteen_gb_mask) - 319 ALIGN(mc->fb_end + 1, sixteen_gb); 320 } 321 322 if (size_bf > size_af) { 323 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 324 mc->agp_size = size_bf; 325 } else { 326 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 327 mc->agp_size = size_af; 328 } 329 330 mc->agp_end = mc->agp_start + mc->agp_size - 1; 331 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 332 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 333 } 334 335 /** 336 * amdgpu_gmc_filter_faults - filter VM faults 337 * 338 * @adev: amdgpu device structure 339 * @addr: address of the VM fault 340 * @pasid: PASID of the process causing the fault 341 * @timestamp: timestamp of the fault 342 * 343 * Returns: 344 * True if the fault was filtered and should not be processed further. 345 * False if the fault is a new one and needs to be handled. 346 */ 347 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 348 uint16_t pasid, uint64_t timestamp) 349 { 350 struct amdgpu_gmc *gmc = &adev->gmc; 351 352 uint64_t stamp, key = addr << 4 | pasid; 353 struct amdgpu_gmc_fault *fault; 354 uint32_t hash; 355 356 /* If we don't have space left in the ring buffer return immediately */ 357 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 358 AMDGPU_GMC_FAULT_TIMEOUT; 359 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 360 return true; 361 362 /* Try to find the fault in the hash */ 363 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 364 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 365 while (fault->timestamp >= stamp) { 366 uint64_t tmp; 367 368 if (fault->key == key) 369 return true; 370 371 tmp = fault->timestamp; 372 fault = &gmc->fault_ring[fault->next]; 373 374 /* Check if the entry was reused */ 375 if (fault->timestamp >= tmp) 376 break; 377 } 378 379 /* Add the fault to the ring */ 380 fault = &gmc->fault_ring[gmc->last_fault]; 381 fault->key = key; 382 fault->timestamp = timestamp; 383 384 /* And update the hash */ 385 fault->next = gmc->fault_hash[hash].idx; 386 gmc->fault_hash[hash].idx = gmc->last_fault++; 387 return false; 388 } 389 390 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 391 { 392 int r; 393 394 if (adev->umc.funcs && adev->umc.funcs->ras_late_init) { 395 r = adev->umc.funcs->ras_late_init(adev); 396 if (r) 397 return r; 398 } 399 400 if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) { 401 r = adev->mmhub.funcs->ras_late_init(adev); 402 if (r) 403 return r; 404 } 405 406 if (!adev->gmc.xgmi.connected_to_cpu) 407 adev->gmc.xgmi.ras_funcs = &xgmi_ras_funcs; 408 409 if (adev->gmc.xgmi.ras_funcs && 410 adev->gmc.xgmi.ras_funcs->ras_late_init) { 411 r = adev->gmc.xgmi.ras_funcs->ras_late_init(adev); 412 if (r) 413 return r; 414 } 415 416 return 0; 417 } 418 419 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 420 { 421 amdgpu_umc_ras_fini(adev); 422 amdgpu_mmhub_ras_fini(adev); 423 if (adev->gmc.xgmi.ras_funcs && 424 adev->gmc.xgmi.ras_funcs->ras_fini) 425 adev->gmc.xgmi.ras_funcs->ras_fini(adev); 426 } 427 428 /* 429 * The latest engine allocation on gfx9/10 is: 430 * Engine 2, 3: firmware 431 * Engine 0, 1, 4~16: amdgpu ring, 432 * subject to change when ring number changes 433 * Engine 17: Gart flushes 434 */ 435 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 436 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 437 438 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 439 { 440 struct amdgpu_ring *ring; 441 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 442 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 443 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 444 unsigned i; 445 unsigned vmhub, inv_eng; 446 447 for (i = 0; i < adev->num_rings; ++i) { 448 ring = adev->rings[i]; 449 vmhub = ring->funcs->vmhub; 450 451 if (ring == &adev->mes.ring) 452 continue; 453 454 inv_eng = ffs(vm_inv_engs[vmhub]); 455 if (!inv_eng) { 456 dev_err(adev->dev, "no VM inv eng for ring %s\n", 457 ring->name); 458 return -EINVAL; 459 } 460 461 ring->vm_inv_eng = inv_eng - 1; 462 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 463 464 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 465 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 466 } 467 468 return 0; 469 } 470 471 /** 472 * amdgpu_tmz_set -- check and set if a device supports TMZ 473 * @adev: amdgpu_device pointer 474 * 475 * Check and set if an the device @adev supports Trusted Memory 476 * Zones (TMZ). 477 */ 478 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 479 { 480 switch (adev->asic_type) { 481 case CHIP_RAVEN: 482 if (amdgpu_tmz == 0) { 483 adev->gmc.tmz_enabled = false; 484 dev_info(adev->dev, 485 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 486 } else { 487 adev->gmc.tmz_enabled = true; 488 dev_info(adev->dev, 489 "Trusted Memory Zone (TMZ) feature enabled\n"); 490 } 491 break; 492 case CHIP_RENOIR: 493 case CHIP_NAVI10: 494 case CHIP_NAVI14: 495 case CHIP_NAVI12: 496 case CHIP_VANGOGH: 497 /* Don't enable it by default yet. 498 */ 499 if (amdgpu_tmz < 1) { 500 adev->gmc.tmz_enabled = false; 501 dev_info(adev->dev, 502 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 503 } else { 504 adev->gmc.tmz_enabled = true; 505 dev_info(adev->dev, 506 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 507 } 508 break; 509 default: 510 adev->gmc.tmz_enabled = false; 511 dev_warn(adev->dev, 512 "Trusted Memory Zone (TMZ) feature not supported\n"); 513 break; 514 } 515 } 516 517 /** 518 * amdgpu_noretry_set -- set per asic noretry defaults 519 * @adev: amdgpu_device pointer 520 * 521 * Set a per asic default for the no-retry parameter. 522 * 523 */ 524 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 525 { 526 struct amdgpu_gmc *gmc = &adev->gmc; 527 528 switch (adev->asic_type) { 529 case CHIP_VEGA10: 530 case CHIP_VEGA20: 531 case CHIP_ARCTURUS: 532 case CHIP_ALDEBARAN: 533 /* 534 * noretry = 0 will cause kfd page fault tests fail 535 * for some ASICs, so set default to 1 for these ASICs. 536 */ 537 if (amdgpu_noretry == -1) 538 gmc->noretry = 1; 539 else 540 gmc->noretry = amdgpu_noretry; 541 break; 542 case CHIP_RAVEN: 543 default: 544 /* Raven currently has issues with noretry 545 * regardless of what we decide for other 546 * asics, we should leave raven with 547 * noretry = 0 until we root cause the 548 * issues. 549 * 550 * default this to 0 for now, but we may want 551 * to change this in the future for certain 552 * GPUs as it can increase performance in 553 * certain cases. 554 */ 555 if (amdgpu_noretry == -1) 556 gmc->noretry = 0; 557 else 558 gmc->noretry = amdgpu_noretry; 559 break; 560 } 561 } 562 563 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 564 bool enable) 565 { 566 struct amdgpu_vmhub *hub; 567 u32 tmp, reg, i; 568 569 hub = &adev->vmhub[hub_type]; 570 for (i = 0; i < 16; i++) { 571 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 572 573 tmp = RREG32(reg); 574 if (enable) 575 tmp |= hub->vm_cntx_cntl_vm_fault; 576 else 577 tmp &= ~hub->vm_cntx_cntl_vm_fault; 578 579 WREG32(reg, tmp); 580 } 581 } 582 583 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 584 { 585 unsigned size; 586 587 /* 588 * TODO: 589 * Currently there is a bug where some memory client outside 590 * of the driver writes to first 8M of VRAM on S3 resume, 591 * this overrides GART which by default gets placed in first 8M and 592 * causes VM_FAULTS once GTT is accessed. 593 * Keep the stolen memory reservation until the while this is not solved. 594 */ 595 switch (adev->asic_type) { 596 case CHIP_VEGA10: 597 case CHIP_RAVEN: 598 case CHIP_RENOIR: 599 adev->mman.keep_stolen_vga_memory = true; 600 break; 601 default: 602 adev->mman.keep_stolen_vga_memory = false; 603 break; 604 } 605 606 if (amdgpu_sriov_vf(adev) || 607 !amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) { 608 size = 0; 609 } else { 610 size = amdgpu_gmc_get_vbios_fb_size(adev); 611 612 if (adev->mman.keep_stolen_vga_memory) 613 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 614 } 615 616 /* set to 0 if the pre-OS buffer uses up most of vram */ 617 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 618 size = 0; 619 620 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 621 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 622 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 623 } else { 624 adev->mman.stolen_vga_size = size; 625 adev->mman.stolen_extended_size = 0; 626 } 627 } 628 629 /** 630 * amdgpu_gmc_init_pdb0 - initialize PDB0 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * This function is only used when GART page table is used 635 * for FB address translatioin. In such a case, we construct 636 * a 2-level system VM page table: PDB0->PTB, to cover both 637 * VRAM of the hive and system memory. 638 * 639 * PDB0 is static, initialized once on driver initialization. 640 * The first n entries of PDB0 are used as PTE by setting 641 * P bit to 1, pointing to VRAM. The n+1'th entry points 642 * to a big PTB covering system memory. 643 * 644 */ 645 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 646 { 647 int i; 648 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 649 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 650 */ 651 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 652 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 653 u64 vram_addr = adev->vm_manager.vram_base_offset - 654 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 655 u64 vram_end = vram_addr + vram_size; 656 u64 gart_ptb_gpu_pa = amdgpu_bo_gpu_offset(adev->gart.bo) + 657 adev->vm_manager.vram_base_offset - adev->gmc.vram_start; 658 659 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 660 flags |= AMDGPU_PTE_WRITEABLE; 661 flags |= AMDGPU_PTE_SNOOPED; 662 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 663 flags |= AMDGPU_PDE_PTE; 664 665 /* The first n PDE0 entries are used as PTE, 666 * pointing to vram 667 */ 668 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 669 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 670 671 /* The n+1'th PDE0 entry points to a huge 672 * PTB who has more than 512 entries each 673 * pointing to a 4K system page 674 */ 675 flags = AMDGPU_PTE_VALID; 676 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 677 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 678 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 679 } 680