clk: renesas: rcar-gen3: Add support for ZG clock

A clock used for the 3D graphics appears to be common
among multiple SoC's, so add a generic gen3 clock
for clocking the graphics. This is similar

clk: renesas: rcar-gen3: Add support for ZG clock

A clock used for the 3D graphics appears to be common
among multiple SoC's, so add a generic gen3 clock
for clocking the graphics. This is similar to the
cpg_z_clk, with a different frequency control register
and different flags. Instead of duplicating the code,
make cpg_z_clk_register into a helper function and
call the help function with the FCR and flags as
a parameter.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-1-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: r8a77995: Add RPC clocks

Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and

clk: renesas: r8a77995: Add RPC clocks

Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and RPC-IF module clock.

The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be

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clk: renesas: rcar-gen3: Add dummy SDnH clock

Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which

clk: renesas: rcar-gen3: Add dummy SDnH clock

Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: r8a774c0: Add RPC clocks

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.

Add n

clk: renesas: r8a774c0: Add RPC clocks

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.

Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed
clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
which has been set prior to booting the kernel.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201116101002.5986-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: Use the correct style for SPDX License Identifier

This patch corrects the SPDX License Identifier style
in header files related to Clock Drivers for Renesas Socs.
For C header files Do

clk: renesas: Use the correct style for SPDX License Identifier

This patch corrects the SPDX License Identifier style
in header files related to Clock Drivers for Renesas Socs.
For C header files Documentation/process/license-rules.rst
mandates C-like comments (opposed to C source files where
C++ style should be used)

Changes made by using a script provided by Joe Perches here:
https://lkml.org/lkml/2019/2/7/46

Suggested-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2

After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redund

clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2

After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redundancy by eliminating the latter.

This is not expected to have any run-time effect.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset

Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.

This is in preparation for supporting the Z2 cloc

clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset

Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor

Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supp

clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor

Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to date.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which has a fixed divisor of 4.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: squashed several patches; rewrote changelog; added r8a774a1 change]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Add RPC clocks

The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different b

clk: renesas: rcar-gen3: Add RPC clocks

The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...

After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: Convert to SPDX identifiers

This patch updates license to use SPDX-License-Identifier
instead of verbose license text.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.c

clk: renesas: Convert to SPDX identifiers

This patch updates license to use SPDX-License-Identifier
instead of verbose license text.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[rebased against clk-spdx]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI

On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car g

clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI

On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
the overridden cpg_clk_register() method; then, finally, add the SD-IF
module clock (derived from the SD0 clock).

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Add support for mode pin clock selection

Make the existing support for selecting between clean and SSCG clocks
using MD12 more generic, to allow using other mode pins for ar

clk: renesas: rcar-gen3: Add support for mode pin clock selection

Make the existing support for selecting between clean and SSCG clocks
using MD12 more generic, to allow using other mode pins for arbitrary
clock selection.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Add support for RCKSEL clock selection

Add a clock type and macro for defining clocks where the parent and
divider are selected based on the value of the RCKCR.CKSEL bit.

S

clk: renesas: rcar-gen3: Add support for RCKSEL clock selection

Add a clock type and macro for defining clocks where the parent and
divider are selected based on the value of the RCKCR.CKSEL bit.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider

Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.

On most R-Car Gen3 SoCs, t

clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider

Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.

On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and
thus must be specified in the configuration structure.

Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Add Z2 clock divider support

This patch adds Z2 clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon

clk: renesas: rcar-gen3: Add Z2 clock divider support

This patch adds Z2 clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Add Z clock divider support

This patch adds Z clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon H

clk: renesas: rcar-gen3: Add Z clock divider support

This patch adds Z clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: cpg-mssr: Add support to restore core clocks during resume

On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly
losing clock configuration. Hence add a notifier ch

clk: renesas: cpg-mssr: Add support to restore core clocks during resume

On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly
losing clock configuration. Hence add a notifier chain that can be used
by core clocks to save/restore clock state during system suspend/resume.

The implementation of the actual clock state save/restore operations is
clock-specific, and to be registered with the notifier chain in the SoC
or family-specific cpg_mssr_info.cpg_clk_register() callback.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

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clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks

On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select

clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks

On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select between clean
and spread spectrum parents.

Add a new clock type to the R-Car Gen3 driver core to handle this.
To avoid increasing the size of struct cpg_core_clk, both parents and
dividers are stored in the existing parent resp. div fields.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>

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clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3

On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one. Extend struct rcar_gen3_cpg_pll_config

clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3

On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one. Extend struct rcar_gen3_cpg_pll_config to handle
this. As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>

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clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()

Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to

clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()

Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()

All R-Car Gen3 clock drivers now obtain the values of the mode pins from
the R-Car RST driver.

Signed-off-by: Geert Uytterhoe

clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()

All R-Car Gen3 clock drivers now obtain the values of the mode pins from
the R-Car RST driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

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clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code

Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-sp

clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code

Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.

Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>

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Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next

- Support for STM32F769
- Rework AT91 sckc DT bindings
- Fix slow RC oscilla

Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next

- Support for STM32F769
- Rework AT91 sckc DT bindings
- Fix slow RC oscillator issue on sama5d3
- AT91 sam9x60 PMC support
- SiFive FU540 PRCI and PLL support

* clk-stm32f4:
clk: stm32mp1: Add ddrperfm clock
clk: stm32: Introduce clocks of STM32F769 board

* clk-tegra:
clk: tegra: divider: Mark Memory Controller clock as read-only
clk: tegra: emc: Replace BUG() with WARN_ONCE()
clk: tegra: emc: Fix EMC max-rate clamping
clk: tegra: emc: Support multiple RAM codes
clk: tegra: emc: Don't enable EMC clock manually
clk: tegra124: Remove lock-enable bit from PLLM
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
clk: tegra: Don't enable already enabled PLLs

* clk-at91:
clk: at91: Mark struct clk_range as const
clk: at91: add sam9x60 pmc driver
dt-bindings: clk: at91: add bindings for SAM9X60 pmc
clk: at91: add sam9x60 PLL driver
clk: at91: master: Add sam9x60 support
clk: at91: usb: Add sam9x60 support
clk: at91: allow configuring generated PCR layout
clk: at91: allow configuring peripheral PCR layout
clk: at91: sckc: handle different RC startup time
clk: at91: modernize sckc binding
dt-bindings: clock: at91: new sckc bindings

* clk-sifive-fu540:
clk: sifive: add a driver for the SiFive FU540 PRCI IP block
clk: analogbits: add Wide-Range PLL library
dt-bindings: clk: add documentation for the SiFive PRCI driver

* clk-spdx:
clk: sunxi-ng: Use the correct style for SPDX License Identifier
clk: sprd: Use the correct style for SPDX License Identifier
clk: renesas: Use the correct style for SPDX License Identifier
clk: qcom: Use the correct style for SPDX License Identifier
clk: davinci: Use the correct style for SPDX License Identifier
clk: actions: Use the correct style for SPDX License Identifier

show more ...

clk: renesas: Use the correct style for SPDX License Identifier

This patch corrects the SPDX License Identifier style
in header files related to Clock Drivers for Renesas Socs.
For C

clk: renesas: Use the correct style for SPDX License Identifier

This patch corrects the SPDX License Identifier style
in header files related to Clock Drivers for Renesas Socs.
For C header files Documentation/process/license-rules.rst
mandates C-like comments (opposed to C source files where
C++ style should be used)

Changes made by using a script provided by Joe Perches here:
https://lkml.org/lkml/2019/2/7/46

Suggested-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2

After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Re

clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2

After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redundancy by eliminating the latter.

This is not expected to have any run-time effect.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

show more ...