1 /*
2  * R-Car Gen3 Clock Pulse Generator
3  *
4  * Copyright (C) 2015-2018 Glider bvba
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  */
10 
11 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
12 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
13 
14 enum rcar_gen3_clk_types {
15 	CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
16 	CLK_TYPE_GEN3_PLL0,
17 	CLK_TYPE_GEN3_PLL1,
18 	CLK_TYPE_GEN3_PLL2,
19 	CLK_TYPE_GEN3_PLL3,
20 	CLK_TYPE_GEN3_PLL4,
21 	CLK_TYPE_GEN3_SD,
22 	CLK_TYPE_GEN3_R,
23 	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */
24 	CLK_TYPE_GEN3_Z,
25 	CLK_TYPE_GEN3_Z2,
26 	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */
27 	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */
28 };
29 
30 #define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
31 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
32 
33 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
34 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL,	\
35 		 (_parent0) << 16 | (_parent1),		\
36 		 .div = (_div0) << 16 | (_div1), .offset = _md)
37 
38 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
39 		    _div_clean) \
40 	DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg,	\
41 		       _parent_clean, _div_clean)
42 
43 #define DEF_GEN3_OSC(_name, _id, _parent, _div)		\
44 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
45 
46 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
47 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,	\
48 		 (_parent0) << 16 | (_parent1),	.div = (_div0) << 16 | (_div1))
49 
50 struct rcar_gen3_cpg_pll_config {
51 	u8 extal_div;
52 	u8 pll1_mult;
53 	u8 pll1_div;
54 	u8 pll3_mult;
55 	u8 pll3_div;
56 	u8 osc_prediv;
57 };
58 
59 #define CPG_RCKCR	0x240
60 
61 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
62 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
63 	struct clk **clks, void __iomem *base,
64 	struct raw_notifier_head *notifiers);
65 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
66 		       unsigned int clk_extalr, u32 mode);
67 
68 #endif
69