1 /* 2 * R-Car Gen3 Clock Pulse Generator 3 * 4 * Copyright (C) 2015-2018 Glider bvba 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 13 14 enum rcar_gen3_clk_types { 15 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 16 CLK_TYPE_GEN3_PLL0, 17 CLK_TYPE_GEN3_PLL1, 18 CLK_TYPE_GEN3_PLL2, 19 CLK_TYPE_GEN3_PLL3, 20 CLK_TYPE_GEN3_PLL4, 21 CLK_TYPE_GEN3_SD, 22 CLK_TYPE_GEN3_R, 23 CLK_TYPE_GEN3_PE, 24 CLK_TYPE_GEN3_Z, 25 CLK_TYPE_GEN3_Z2, 26 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 28 }; 29 30 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 31 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 32 33 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 34 _div_clean) \ 35 DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ 36 (_parent_sscg) << 16 | (_parent_clean), \ 37 .div = (_div_sscg) << 16 | (_div_clean)) 38 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 39 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 40 41 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 42 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 43 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 44 45 struct rcar_gen3_cpg_pll_config { 46 u8 extal_div; 47 u8 pll1_mult; 48 u8 pll1_div; 49 u8 pll3_mult; 50 u8 pll3_div; 51 u8 osc_prediv; 52 }; 53 54 #define CPG_RCKCR 0x240 55 56 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 57 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 58 struct clk **clks, void __iomem *base, 59 struct raw_notifier_head *notifiers); 60 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 61 unsigned int clk_extalr, u32 mode); 62 63 #endif 64