MIPS: Lantiq: Add clock for mei driver

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwor

MIPS: Lantiq: Add clock for mei driver

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11391/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: Lantiq: Add pmu bits for ar10 and grx390

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://

MIPS: Lantiq: Add pmu bits for ar10 and grx390

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11388/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: Lantiq: Add PMU bits for USB and SDIO devices

This adds the PUM bits for USB and SDIO devices

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.

MIPS: Lantiq: Add PMU bits for USB and SDIO devices

This adds the PUM bits for USB and SDIO devices

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11387/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: Lantiq: Deactivate most of the devices by default

When the SoC starts up most of the devices should be deactivated by the
PMU, they should be activated when they get used by their drivers. Som

MIPS: Lantiq: Deactivate most of the devices by default

When the SoC starts up most of the devices should be deactivated by the
PMU, they should be activated when they get used by their drivers. Some
devices should not get deactivate at startup like the serial, register
them in a special way.

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11386/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: Lantiq: Add support for setting PMU register on AR10 and GRX390

This adds support for setting the PMU register on the AR10 and GRX390.

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com

MIPS: Lantiq: Add support for setting PMU register on AR10 and GRX390

This adds support for setting the PMU register on the AR10 and GRX390.

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11382/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: Lantiq: Add locking for PMU register and check status afterwards

The PMU register are accessed in a non atomic way and they could be
accessed by different threads simultaneously, which could c

MIPS: Lantiq: Add locking for PMU register and check status afterwards

The PMU register are accessed in a non atomic way and they could be
accessed by different threads simultaneously, which could cause
problems this patch adds locking around the PMU registers. In
addition we now also wait till the PMU is actually deactivated.

[ralf@linux-mips.org: Fix spelling mistake in commit message as noticed
by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>.]

Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11381/
Patchwork: https://patchwork.linux-mips.org/patch/11396/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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treewide: fix errors in printk

This patch fix spelling typo in printk.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Randy Dunla

treewide: fix errors in printk

This patch fix spelling typo in printk.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

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MIPS: Panic messages should not end in \n.

Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.

Signed-off-by: Ralf Baechle <

MIPS: Panic messages should not end in \n.

Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: lantiq: add GPHY clock gate bits

Explicitly enable the clock gate of the internal GPHYs found on xrx200.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mip

MIPS: lantiq: add GPHY clock gate bits

Explicitly enable the clock gate of the internal GPHYs found on xrx200.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/

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MIPS: lantiq: adds static clock for PP32

The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwor

MIPS: lantiq: adds static clock for PP32

The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4815/

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MIPS: lantiq: trivial typo fix

"nodes" is written with a single "s"

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4814/

MIPS: lantiq: adds xrx200 ethernet clock definition

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4521

MIPS: lantiq: enable pci clk conditional for xrx200 SoC

The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic

MIPS: lantiq: enable pci clk conditional for xrx200 SoC

The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/

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MIPS: lantiq: explicitly enable clkout generation

Previously we relied on the bootloader to have enabled this bit. However some
bootloaders seem to not enable this for us.

Signed-off-by: John Crisp

MIPS: lantiq: explicitly enable clkout generation

Previously we relied on the bootloader to have enabled this bit. However some
bootloaders seem to not enable this for us.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4120/

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MIPS: Lantiq: Fix interface clock and PCI control register offset

The XRX200 based SoC have a different register offset for the interface
clock and PCI control registers. This patch detects the SoC

MIPS: Lantiq: Fix interface clock and PCI control register offset

The XRX200 based SoC have a different register offset for the interface
clock and PCI control registers. This patch detects the SoC and sets the
register offset at runtime. This make PCI work on the VR9 SoC.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4113/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: lantiq: remove orphaned code

Now that all drivers are converted to OF we are able to remove some remaining
pieces of orphaned code.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-

MIPS: lantiq: remove orphaned code

Now that all drivers are converted to OF we are able to remove some remaining
pieces of orphaned code.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: lantiq: implement support for clkdev api

This patch unifies all clock generation and gating code into one file.
All drivers will now be able to request their clocks via their device.
This patc

MIPS: lantiq: implement support for clkdev api

This patch unifies all clock generation and gating code into one file.
All drivers will now be able to request their clocks via their device.
This patch also adds support for the clockout feature, which allows
clock generation on external pins.

Support for COMMON_CLK will be provided in the next series.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3804/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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MIPS: lantiq: add missing GPHY clock aliases for ar10 and grx390

Add missing GPHY clock aliases for ar10 (xrx300) and grx390 (xrx330).
PMU in ar10 and grx390 differs from vr9. Ar10 has 3

MIPS: lantiq: add missing GPHY clock aliases for ar10 and grx390

Add missing GPHY clock aliases for ar10 (xrx300) and grx390 (xrx330).
PMU in ar10 and grx390 differs from vr9. Ar10 has 3 and grx390 has 4
built-in GPHY compared to vr9 which has 2.

Corespondings PMU bit:
GPHY0 -> bit 29
GPHY1 -> bit 30
GPHY2 -> bit 31
GPHY3 -> bit 26

Tested on D-Link DWR-966 with OpenWRT.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Cc: linux-mips@vger.kernel.org
Cc: john@phrozen.org
Cc: hauke@hauke-m.de
Cc: tsbogend@alpha.franken.de
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

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MIPS: lantiq: xway: sysctrl: fix the GPHY clock alias names

The dt-bindings for the GSWIP describe that the node should be named
"switch". Use the same name in sysctrl.c so the GSWIP dri

MIPS: lantiq: xway: sysctrl: fix the GPHY clock alias names

The dt-bindings for the GSWIP describe that the node should be named
"switch". Use the same name in sysctrl.c so the GSWIP driver can
actually find the "gphy0" and "gphy1" clocks.

Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Cc: stable@vger.kernel.org
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

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remove ioremap_nocache and devm_ioremap_nocache

ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.

remove ioremap_nocache and devm_ioremap_nocache

ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>

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MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

The mainline PCIe PHY driver has it's own devicetree node. Update the
clock alias so the mainline driver finds the

MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

The mainline PCIe PHY driver has it's own devicetree node. Update the
clock alias so the mainline driver finds the clocks.

The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
and GRX390.
The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
GRX390.
The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
Lantiq's board support package (called "UGW") names these registers
"PDI".

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: john@phrozen.org
Cc: kishon@ti.com
Cc: ralf@linux-mips.org
Cc: robh+dt@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: hauke@hauke-m.de
Cc: mark.rutland@arm.com
Cc: ms@dev.tdt.de

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it u

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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net: dsa: Add Lantiq / Intel DSA driver for vrx200

This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC.
This switch is integrated in the DSL SoC, this SoC uses a GSWIP

net: dsa: Add Lantiq / Intel DSA driver for vrx200

This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC.
This switch is integrated in the DSL SoC, this SoC uses a GSWIP version
2.1, there are other SoCs using different versions of this IP block, but
this driver was only tested with the version found in the VRX200.
Currently only the basic features are implemented which will forward all
packages to the CPU and let the CPU do the forwarding. The hardware also
support Layer 2 offloading which is not yet implemented in this driver.

The GPHY FW loaded is now done by this driver and not any more by the
separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver
is a separate patch. to make use of the GPHY this switch driver is
needed anyway. Other SoCs have more embedded GPHYs so this driver should
support a variable number of GPHYs. After the firmware was loaded the
GPHY can be probed on the MDIO bus and it behaves like an external GPHY,
without the firmware it can not be probed on the MDIO bus.

The clock names in the sysctrl.c file have to be changed because the
clocks are now used by a different driver. This should be cleaned up and
a real common clock driver should provide the clocks instead.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: David S. Miller <davem@davemloft.net>

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net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver

This drives the PMAC between the GSWIP Switch and the CPU in the VRX200
SoC. This is currently only the very basic version of the E

net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver

This drives the PMAC between the GSWIP Switch and the CPU in the VRX200
SoC. This is currently only the very basic version of the Ethernet
driver.

When the DMA channel is activated we receive some packets which were
send to the SoC while it was still in U-Boot, these packets have the
wrong header. Resetting the IP cores did not work so we read out the
extra packets at the beginning and discard them.

This also adapts the clock code in sysctrl.c to use the default name of
the device node so that the driver gets the correct clock. sysctrl.c
should be replaced with a proper common clock driver later.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: David S. Miller <davem@davemloft.net>

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MIPS: lantiq: Enable AHB Bus for USB

On Danube and AR9 the USB core is connected though a AHB bus to the main
system cross bar, hence we need to enable the gating clock of the AHB
Bu

MIPS: lantiq: Enable AHB Bus for USB

On Danube and AR9 the USB core is connected though a AHB bus to the main
system cross bar, hence we need to enable the gating clock of the AHB
Bus as well to make the USB controller work.

Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module")
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.14+
Patchwork: https://patchwork.linux-mips.org/patch/18814/
Signed-off-by: James Hogan <jhogan@kernel.org>

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