1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org> 7 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG 8 */ 9 10 #include <linux/ioport.h> 11 #include <linux/export.h> 12 #include <linux/clkdev.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/of_address.h> 16 17 #include <lantiq_soc.h> 18 19 #include "../clk.h" 20 #include "../prom.h" 21 22 /* clock control register */ 23 #define CGU_IFCCR 0x0018 24 #define CGU_IFCCR_VR9 0x0024 25 /* system clock register */ 26 #define CGU_SYS 0x0010 27 /* pci control register */ 28 #define CGU_PCICR 0x0034 29 #define CGU_PCICR_VR9 0x0038 30 /* ephy configuration register */ 31 #define CGU_EPHY 0x10 32 /* power control register */ 33 #define PMU_PWDCR 0x1C 34 /* power status register */ 35 #define PMU_PWDSR 0x20 36 /* power control register */ 37 #define PMU_PWDCR1 0x24 38 /* power status register */ 39 #define PMU_PWDSR1 0x28 40 /* power control register */ 41 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) 42 /* power status register */ 43 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) 44 45 /* clock gates that we can en/disable */ 46 #define PMU_USB0_P BIT(0) 47 #define PMU_PCI BIT(4) 48 #define PMU_DMA BIT(5) 49 #define PMU_USB0 BIT(6) 50 #define PMU_ASC0 BIT(7) 51 #define PMU_EPHY BIT(7) /* ase */ 52 #define PMU_SPI BIT(8) 53 #define PMU_DFE BIT(9) 54 #define PMU_EBU BIT(10) 55 #define PMU_STP BIT(11) 56 #define PMU_GPT BIT(12) 57 #define PMU_AHBS BIT(13) /* vr9 */ 58 #define PMU_FPI BIT(14) 59 #define PMU_AHBM BIT(15) 60 #define PMU_ASC1 BIT(17) 61 #define PMU_PPE_QSB BIT(18) 62 #define PMU_PPE_SLL01 BIT(19) 63 #define PMU_PPE_TC BIT(21) 64 #define PMU_PPE_EMA BIT(22) 65 #define PMU_PPE_DPLUM BIT(23) 66 #define PMU_PPE_DPLUS BIT(24) 67 #define PMU_USB1_P BIT(26) 68 #define PMU_USB1 BIT(27) 69 #define PMU_SWITCH BIT(28) 70 #define PMU_PPE_TOP BIT(29) 71 #define PMU_GPHY BIT(30) 72 #define PMU_PCIE_CLK BIT(31) 73 74 #define PMU1_PCIE_PHY BIT(0) 75 #define PMU1_PCIE_CTL BIT(1) 76 #define PMU1_PCIE_PDI BIT(4) 77 #define PMU1_PCIE_MSI BIT(5) 78 79 #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y)) 80 #define pmu_r32(x) ltq_r32(pmu_membase + (x)) 81 82 static void __iomem *pmu_membase; 83 void __iomem *ltq_cgu_membase; 84 void __iomem *ltq_ebu_membase; 85 86 static u32 ifccr = CGU_IFCCR; 87 static u32 pcicr = CGU_PCICR; 88 89 static DEFINE_SPINLOCK(g_pmu_lock); 90 91 /* legacy function kept alive to ease clkdev transition */ 92 void ltq_pmu_enable(unsigned int module) 93 { 94 int retry = 1000000; 95 96 spin_lock(&g_pmu_lock); 97 pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); 98 do {} while (--retry && (pmu_r32(PMU_PWDSR) & module)); 99 spin_unlock(&g_pmu_lock); 100 101 if (!retry) 102 panic("activating PMU module failed!"); 103 } 104 EXPORT_SYMBOL(ltq_pmu_enable); 105 106 /* legacy function kept alive to ease clkdev transition */ 107 void ltq_pmu_disable(unsigned int module) 108 { 109 int retry = 1000000; 110 111 spin_lock(&g_pmu_lock); 112 pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); 113 do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module))); 114 spin_unlock(&g_pmu_lock); 115 116 if (!retry) 117 pr_warn("deactivating PMU module failed!"); 118 } 119 EXPORT_SYMBOL(ltq_pmu_disable); 120 121 /* enable a hw clock */ 122 static int cgu_enable(struct clk *clk) 123 { 124 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); 125 return 0; 126 } 127 128 /* disable a hw clock */ 129 static void cgu_disable(struct clk *clk) 130 { 131 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); 132 } 133 134 /* enable a clock gate */ 135 static int pmu_enable(struct clk *clk) 136 { 137 int retry = 1000000; 138 139 spin_lock(&g_pmu_lock); 140 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, 141 PWDCR(clk->module)); 142 do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); 143 spin_unlock(&g_pmu_lock); 144 145 if (!retry) 146 panic("activating PMU module failed!"); 147 148 return 0; 149 } 150 151 /* disable a clock gate */ 152 static void pmu_disable(struct clk *clk) 153 { 154 int retry = 1000000; 155 156 spin_lock(&g_pmu_lock); 157 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, PWDCR(clk->module)); 158 do {} while (--retry && (!(pmu_r32(PWDSR(clk->module)) & clk->bits))); 159 spin_unlock(&g_pmu_lock); 160 161 if (!retry) 162 pr_warn("deactivating PMU module failed!"); 163 } 164 165 /* the pci enable helper */ 166 static int pci_enable(struct clk *clk) 167 { 168 unsigned int val = ltq_cgu_r32(ifccr); 169 /* set bus clock speed */ 170 if (of_machine_is_compatible("lantiq,ar9") || 171 of_machine_is_compatible("lantiq,vr9")) { 172 val &= ~0x1f00000; 173 if (clk->rate == CLOCK_33M) 174 val |= 0xe00000; 175 else 176 val |= 0x700000; /* 62.5M */ 177 } else { 178 val &= ~0xf00000; 179 if (clk->rate == CLOCK_33M) 180 val |= 0x800000; 181 else 182 val |= 0x400000; /* 62.5M */ 183 } 184 ltq_cgu_w32(val, ifccr); 185 pmu_enable(clk); 186 return 0; 187 } 188 189 /* enable the external clock as a source */ 190 static int pci_ext_enable(struct clk *clk) 191 { 192 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); 193 ltq_cgu_w32((1 << 30), pcicr); 194 return 0; 195 } 196 197 /* disable the external clock as a source */ 198 static void pci_ext_disable(struct clk *clk) 199 { 200 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); 201 ltq_cgu_w32((1 << 31) | (1 << 30), pcicr); 202 } 203 204 /* enable a clockout source */ 205 static int clkout_enable(struct clk *clk) 206 { 207 int i; 208 209 /* get the correct rate */ 210 for (i = 0; i < 4; i++) { 211 if (clk->rates[i] == clk->rate) { 212 int shift = 14 - (2 * clk->module); 213 int enable = 7 - clk->module; 214 unsigned int val = ltq_cgu_r32(ifccr); 215 216 val &= ~(3 << shift); 217 val |= i << shift; 218 val |= enable; 219 ltq_cgu_w32(val, ifccr); 220 return 0; 221 } 222 } 223 return -1; 224 } 225 226 /* manage the clock gates via PMU */ 227 static void clkdev_add_pmu(const char *dev, const char *con, 228 unsigned int module, unsigned int bits) 229 { 230 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 231 232 clk->cl.dev_id = dev; 233 clk->cl.con_id = con; 234 clk->cl.clk = clk; 235 clk->enable = pmu_enable; 236 clk->disable = pmu_disable; 237 clk->module = module; 238 clk->bits = bits; 239 clkdev_add(&clk->cl); 240 } 241 242 /* manage the clock generator */ 243 static void clkdev_add_cgu(const char *dev, const char *con, 244 unsigned int bits) 245 { 246 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 247 248 clk->cl.dev_id = dev; 249 clk->cl.con_id = con; 250 clk->cl.clk = clk; 251 clk->enable = cgu_enable; 252 clk->disable = cgu_disable; 253 clk->bits = bits; 254 clkdev_add(&clk->cl); 255 } 256 257 /* pci needs its own enable function as the setup is a bit more complex */ 258 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0}; 259 260 static void clkdev_add_pci(void) 261 { 262 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 263 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); 264 265 /* main pci clock */ 266 clk->cl.dev_id = "17000000.pci"; 267 clk->cl.con_id = NULL; 268 clk->cl.clk = clk; 269 clk->rate = CLOCK_33M; 270 clk->rates = valid_pci_rates; 271 clk->enable = pci_enable; 272 clk->disable = pmu_disable; 273 clk->module = 0; 274 clk->bits = PMU_PCI; 275 clkdev_add(&clk->cl); 276 277 /* use internal/external bus clock */ 278 clk_ext->cl.dev_id = "17000000.pci"; 279 clk_ext->cl.con_id = "external"; 280 clk_ext->cl.clk = clk_ext; 281 clk_ext->enable = pci_ext_enable; 282 clk_ext->disable = pci_ext_disable; 283 clkdev_add(&clk_ext->cl); 284 } 285 286 /* xway socs can generate clocks on gpio pins */ 287 static unsigned long valid_clkout_rates[4][5] = { 288 {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, 289 {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0}, 290 {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0}, 291 {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0}, 292 }; 293 294 static void clkdev_add_clkout(void) 295 { 296 int i; 297 298 for (i = 0; i < 4; i++) { 299 struct clk *clk; 300 char *name; 301 302 name = kzalloc(sizeof("clkout0"), GFP_KERNEL); 303 sprintf(name, "clkout%d", i); 304 305 clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 306 clk->cl.dev_id = "1f103000.cgu"; 307 clk->cl.con_id = name; 308 clk->cl.clk = clk; 309 clk->rate = 0; 310 clk->rates = valid_clkout_rates[i]; 311 clk->enable = clkout_enable; 312 clk->module = i; 313 clkdev_add(&clk->cl); 314 } 315 } 316 317 /* bring up all register ranges that we need for basic system control */ 318 void __init ltq_soc_init(void) 319 { 320 struct resource res_pmu, res_cgu, res_ebu; 321 struct device_node *np_pmu = 322 of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway"); 323 struct device_node *np_cgu = 324 of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway"); 325 struct device_node *np_ebu = 326 of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway"); 327 328 /* check if all the core register ranges are available */ 329 if (!np_pmu || !np_cgu || !np_ebu) 330 panic("Failed to load core nodes from devicetree"); 331 332 if (of_address_to_resource(np_pmu, 0, &res_pmu) || 333 of_address_to_resource(np_cgu, 0, &res_cgu) || 334 of_address_to_resource(np_ebu, 0, &res_ebu)) 335 panic("Failed to get core resources"); 336 337 if ((request_mem_region(res_pmu.start, resource_size(&res_pmu), 338 res_pmu.name) < 0) || 339 (request_mem_region(res_cgu.start, resource_size(&res_cgu), 340 res_cgu.name) < 0) || 341 (request_mem_region(res_ebu.start, resource_size(&res_ebu), 342 res_ebu.name) < 0)) 343 pr_err("Failed to request core resources"); 344 345 pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu)); 346 ltq_cgu_membase = ioremap_nocache(res_cgu.start, 347 resource_size(&res_cgu)); 348 ltq_ebu_membase = ioremap_nocache(res_ebu.start, 349 resource_size(&res_ebu)); 350 if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase) 351 panic("Failed to remap core resources"); 352 353 /* make sure to unprotect the memory region where flash is located */ 354 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); 355 356 /* add our generic xway clocks */ 357 clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI); 358 clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0); 359 clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT); 360 clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP); 361 clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA); 362 clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI); 363 clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU); 364 clkdev_add_clkout(); 365 366 /* add the soc dependent clocks */ 367 if (of_machine_is_compatible("lantiq,vr9")) { 368 ifccr = CGU_IFCCR_VR9; 369 pcicr = CGU_PCICR_VR9; 370 } else { 371 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE); 372 } 373 374 if (!of_machine_is_compatible("lantiq,ase")) { 375 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1); 376 clkdev_add_pci(); 377 } 378 379 if (of_machine_is_compatible("lantiq,ase")) { 380 if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) 381 clkdev_add_static(CLOCK_266M, CLOCK_133M, 382 CLOCK_133M, CLOCK_266M); 383 else 384 clkdev_add_static(CLOCK_133M, CLOCK_133M, 385 CLOCK_133M, CLOCK_133M); 386 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY), 387 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY); 388 } else if (of_machine_is_compatible("lantiq,vr9")) { 389 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 390 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz()); 391 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); 392 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); 393 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); 394 clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); 395 clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); 396 clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); 397 clkdev_add_pmu("1e108000.eth", NULL, 0, 398 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 399 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 400 PMU_PPE_QSB | PMU_PPE_TOP); 401 clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY); 402 } else if (of_machine_is_compatible("lantiq,ar9")) { 403 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 404 ltq_ar9_fpi_hz(), CLOCK_250M); 405 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH); 406 } else { 407 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 408 ltq_danube_fpi_hz(), ltq_danube_pp32_hz()); 409 } 410 } 411