1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU102 RevA 4 * 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU102 RevA"; 21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 nvmem0 = &eeprom; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 }; 34 35 chosen { 36 bootargs = "earlycon"; 37 stdout-path = "serial0:115200n8"; 38 }; 39 40 memory@0 { 41 device_type = "memory"; 42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 autorepeat; 48 sw19 { 49 label = "sw19"; 50 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 51 linux,code = <KEY_DOWN>; 52 wakeup-source; 53 autorepeat; 54 }; 55 }; 56 57 leds { 58 compatible = "gpio-leds"; 59 heartbeat-led { 60 label = "heartbeat"; 61 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 62 linux,default-trigger = "heartbeat"; 63 }; 64 }; 65 66 ina226-u76 { 67 compatible = "iio-hwmon"; 68 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 69 }; 70 ina226-u77 { 71 compatible = "iio-hwmon"; 72 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 73 }; 74 ina226-u78 { 75 compatible = "iio-hwmon"; 76 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 77 }; 78 ina226-u87 { 79 compatible = "iio-hwmon"; 80 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 81 }; 82 ina226-u85 { 83 compatible = "iio-hwmon"; 84 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 85 }; 86 ina226-u86 { 87 compatible = "iio-hwmon"; 88 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 89 }; 90 ina226-u93 { 91 compatible = "iio-hwmon"; 92 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 93 }; 94 ina226-u88 { 95 compatible = "iio-hwmon"; 96 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 97 }; 98 ina226-u15 { 99 compatible = "iio-hwmon"; 100 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 101 }; 102 ina226-u92 { 103 compatible = "iio-hwmon"; 104 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 105 }; 106 ina226-u79 { 107 compatible = "iio-hwmon"; 108 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 109 }; 110 ina226-u81 { 111 compatible = "iio-hwmon"; 112 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 113 }; 114 ina226-u80 { 115 compatible = "iio-hwmon"; 116 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 117 }; 118 ina226-u84 { 119 compatible = "iio-hwmon"; 120 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 121 }; 122 ina226-u16 { 123 compatible = "iio-hwmon"; 124 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 125 }; 126 ina226-u65 { 127 compatible = "iio-hwmon"; 128 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 129 }; 130 ina226-u74 { 131 compatible = "iio-hwmon"; 132 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 133 }; 134 ina226-u75 { 135 compatible = "iio-hwmon"; 136 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 137 }; 138 139 /* 48MHz reference crystal */ 140 ref48: ref48M { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <48000000>; 144 }; 145 146 refhdmi: refhdmi { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <114285000>; 150 }; 151}; 152 153&can1 { 154 status = "okay"; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_can1_default>; 157}; 158 159&dcc { 160 status = "okay"; 161}; 162 163&fpd_dma_chan1 { 164 status = "okay"; 165}; 166 167&fpd_dma_chan2 { 168 status = "okay"; 169}; 170 171&fpd_dma_chan3 { 172 status = "okay"; 173}; 174 175&fpd_dma_chan4 { 176 status = "okay"; 177}; 178 179&fpd_dma_chan5 { 180 status = "okay"; 181}; 182 183&fpd_dma_chan6 { 184 status = "okay"; 185}; 186 187&fpd_dma_chan7 { 188 status = "okay"; 189}; 190 191&fpd_dma_chan8 { 192 status = "okay"; 193}; 194 195&gem3 { 196 status = "okay"; 197 phy-handle = <&phy0>; 198 phy-mode = "rgmii-id"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_gem3_default>; 201 phy0: ethernet-phy@21 { 202 reg = <21>; 203 ti,rx-internal-delay = <0x8>; 204 ti,tx-internal-delay = <0xa>; 205 ti,fifo-depth = <0x1>; 206 ti,dp83867-rxctrl-strap-quirk; 207 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ 208 }; 209}; 210 211&gpio { 212 status = "okay"; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_gpio_default>; 215}; 216 217&i2c0 { 218 status = "okay"; 219 clock-frequency = <400000>; 220 pinctrl-names = "default", "gpio"; 221 pinctrl-0 = <&pinctrl_i2c0_default>; 222 pinctrl-1 = <&pinctrl_i2c0_gpio>; 223 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 224 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 225 226 tca6416_u97: gpio@20 { 227 compatible = "ti,tca6416"; 228 reg = <0x20>; 229 gpio-controller; /* IRQ not connected */ 230 #gpio-cells = <2>; 231 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", 232 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", 233 "", "", "", "", "", "", "", "", ""; 234 gtr-sel0-hog { 235 gpio-hog; 236 gpios = <0 0>; 237 output-low; /* PCIE = 0, DP = 1 */ 238 line-name = "sel0"; 239 }; 240 gtr-sel1-hog { 241 gpio-hog; 242 gpios = <1 0>; 243 output-high; /* PCIE = 0, DP = 1 */ 244 line-name = "sel1"; 245 }; 246 gtr-sel2-hog { 247 gpio-hog; 248 gpios = <2 0>; 249 output-high; /* PCIE = 0, USB0 = 1 */ 250 line-name = "sel2"; 251 }; 252 gtr-sel3-hog { 253 gpio-hog; 254 gpios = <3 0>; 255 output-high; /* PCIE = 0, SATA = 1 */ 256 line-name = "sel3"; 257 }; 258 }; 259 260 tca6416_u61: gpio@21 { 261 compatible = "ti,tca6416"; 262 reg = <0x21>; 263 gpio-controller; /* IRQ not connected */ 264 #gpio-cells = <2>; 265 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", 266 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", 267 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", 268 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; 269 }; 270 271 i2c-mux@75 { /* u60 */ 272 compatible = "nxp,pca9544"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0x75>; 276 i2c@0 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 reg = <0>; 280 /* PS_PMBUS */ 281 u76: ina226@40 { /* u76 */ 282 compatible = "ti,ina226"; 283 #io-channel-cells = <1>; 284 label = "ina226-u76"; 285 reg = <0x40>; 286 shunt-resistor = <5000>; 287 }; 288 u77: ina226@41 { /* u77 */ 289 compatible = "ti,ina226"; 290 #io-channel-cells = <1>; 291 label = "ina226-u77"; 292 reg = <0x41>; 293 shunt-resistor = <5000>; 294 }; 295 u78: ina226@42 { /* u78 */ 296 compatible = "ti,ina226"; 297 #io-channel-cells = <1>; 298 label = "ina226-u78"; 299 reg = <0x42>; 300 shunt-resistor = <5000>; 301 }; 302 u87: ina226@43 { /* u87 */ 303 compatible = "ti,ina226"; 304 #io-channel-cells = <1>; 305 label = "ina226-u87"; 306 reg = <0x43>; 307 shunt-resistor = <5000>; 308 }; 309 u85: ina226@44 { /* u85 */ 310 compatible = "ti,ina226"; 311 #io-channel-cells = <1>; 312 label = "ina226-u85"; 313 reg = <0x44>; 314 shunt-resistor = <5000>; 315 }; 316 u86: ina226@45 { /* u86 */ 317 compatible = "ti,ina226"; 318 #io-channel-cells = <1>; 319 label = "ina226-u86"; 320 reg = <0x45>; 321 shunt-resistor = <5000>; 322 }; 323 u93: ina226@46 { /* u93 */ 324 compatible = "ti,ina226"; 325 #io-channel-cells = <1>; 326 label = "ina226-u93"; 327 reg = <0x46>; 328 shunt-resistor = <5000>; 329 }; 330 u88: ina226@47 { /* u88 */ 331 compatible = "ti,ina226"; 332 #io-channel-cells = <1>; 333 label = "ina226-u88"; 334 reg = <0x47>; 335 shunt-resistor = <5000>; 336 }; 337 u15: ina226@4a { /* u15 */ 338 compatible = "ti,ina226"; 339 #io-channel-cells = <1>; 340 label = "ina226-u15"; 341 reg = <0x4a>; 342 shunt-resistor = <5000>; 343 }; 344 u92: ina226@4b { /* u92 */ 345 compatible = "ti,ina226"; 346 #io-channel-cells = <1>; 347 label = "ina226-u92"; 348 reg = <0x4b>; 349 shunt-resistor = <5000>; 350 }; 351 }; 352 i2c@1 { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 reg = <1>; 356 /* PL_PMBUS */ 357 u79: ina226@40 { /* u79 */ 358 compatible = "ti,ina226"; 359 #io-channel-cells = <1>; 360 label = "ina226-u79"; 361 reg = <0x40>; 362 shunt-resistor = <2000>; 363 }; 364 u81: ina226@41 { /* u81 */ 365 compatible = "ti,ina226"; 366 #io-channel-cells = <1>; 367 label = "ina226-u81"; 368 reg = <0x41>; 369 shunt-resistor = <5000>; 370 }; 371 u80: ina226@42 { /* u80 */ 372 compatible = "ti,ina226"; 373 #io-channel-cells = <1>; 374 label = "ina226-u80"; 375 reg = <0x42>; 376 shunt-resistor = <5000>; 377 }; 378 u84: ina226@43 { /* u84 */ 379 compatible = "ti,ina226"; 380 #io-channel-cells = <1>; 381 label = "ina226-u84"; 382 reg = <0x43>; 383 shunt-resistor = <5000>; 384 }; 385 u16: ina226@44 { /* u16 */ 386 compatible = "ti,ina226"; 387 #io-channel-cells = <1>; 388 label = "ina226-u16"; 389 reg = <0x44>; 390 shunt-resistor = <5000>; 391 }; 392 u65: ina226@45 { /* u65 */ 393 compatible = "ti,ina226"; 394 #io-channel-cells = <1>; 395 label = "ina226-u65"; 396 reg = <0x45>; 397 shunt-resistor = <5000>; 398 }; 399 u74: ina226@46 { /* u74 */ 400 compatible = "ti,ina226"; 401 #io-channel-cells = <1>; 402 label = "ina226-u74"; 403 reg = <0x46>; 404 shunt-resistor = <5000>; 405 }; 406 u75: ina226@47 { /* u75 */ 407 compatible = "ti,ina226"; 408 #io-channel-cells = <1>; 409 label = "ina226-u75"; 410 reg = <0x47>; 411 shunt-resistor = <5000>; 412 }; 413 }; 414 i2c@2 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 reg = <2>; 418 /* MAXIM_PMBUS - 00 */ 419 max15301@a { /* u46 */ 420 compatible = "maxim,max15301"; 421 reg = <0xa>; 422 }; 423 max15303@b { /* u4 */ 424 compatible = "maxim,max15303"; 425 reg = <0xb>; 426 }; 427 max15303@10 { /* u13 */ 428 compatible = "maxim,max15303"; 429 reg = <0x10>; 430 }; 431 max15301@13 { /* u47 */ 432 compatible = "maxim,max15301"; 433 reg = <0x13>; 434 }; 435 max15303@14 { /* u7 */ 436 compatible = "maxim,max15303"; 437 reg = <0x14>; 438 }; 439 max15303@15 { /* u6 */ 440 compatible = "maxim,max15303"; 441 reg = <0x15>; 442 }; 443 max15303@16 { /* u10 */ 444 compatible = "maxim,max15303"; 445 reg = <0x16>; 446 }; 447 max15303@17 { /* u9 */ 448 compatible = "maxim,max15303"; 449 reg = <0x17>; 450 }; 451 max15301@18 { /* u63 */ 452 compatible = "maxim,max15301"; 453 reg = <0x18>; 454 }; 455 max15303@1a { /* u49 */ 456 compatible = "maxim,max15303"; 457 reg = <0x1a>; 458 }; 459 max15303@1d { /* u18 */ 460 compatible = "maxim,max15303"; 461 reg = <0x1d>; 462 }; 463 max15303@20 { /* u8 */ 464 compatible = "maxim,max15303"; 465 status = "disabled"; /* unreachable */ 466 reg = <0x20>; 467 }; 468 max20751@72 { /* u95 */ 469 compatible = "maxim,max20751"; 470 reg = <0x72>; 471 }; 472 max20751@73 { /* u96 */ 473 compatible = "maxim,max20751"; 474 reg = <0x73>; 475 }; 476 }; 477 /* Bus 3 is not connected */ 478 }; 479}; 480 481&i2c1 { 482 status = "okay"; 483 clock-frequency = <400000>; 484 pinctrl-names = "default", "gpio"; 485 pinctrl-0 = <&pinctrl_i2c1_default>; 486 pinctrl-1 = <&pinctrl_i2c1_gpio>; 487 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 488 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 489 490 /* PL i2c via PCA9306 - u45 */ 491 i2c-mux@74 { /* u34 */ 492 compatible = "nxp,pca9548"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <0x74>; 496 i2c@0 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 reg = <0>; 500 /* 501 * IIC_EEPROM 1kB memory which uses 256B blocks 502 * where every block has different address. 503 * 0 - 256B address 0x54 504 * 256B - 512B address 0x55 505 * 512B - 768B address 0x56 506 * 768B - 1024B address 0x57 507 */ 508 eeprom: eeprom@54 { /* u23 */ 509 compatible = "atmel,24c08"; 510 reg = <0x54>; 511 }; 512 }; 513 i2c@1 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <1>; 517 si5341: clock-generator@36 { /* SI5341 - u69 */ 518 compatible = "silabs,si5341"; 519 reg = <0x36>; 520 #clock-cells = <2>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 clocks = <&ref48>; 524 clock-names = "xtal"; 525 clock-output-names = "si5341"; 526 527 si5341_0: out@0 { 528 /* refclk0 for PS-GT, used for DP */ 529 reg = <0>; 530 always-on; 531 }; 532 si5341_2: out@2 { 533 /* refclk2 for PS-GT, used for USB3 */ 534 reg = <2>; 535 always-on; 536 }; 537 si5341_3: out@3 { 538 /* refclk3 for PS-GT, used for SATA */ 539 reg = <3>; 540 always-on; 541 }; 542 si5341_4: out@4 { 543 /* refclk4 for PS-GT, used for PCIE slot */ 544 reg = <4>; 545 always-on; 546 }; 547 si5341_5: out@5 { 548 /* refclk5 for PS-GT, used for PCIE */ 549 reg = <5>; 550 always-on; 551 }; 552 si5341_6: out@6 { 553 /* refclk6 PL CLK125 */ 554 reg = <6>; 555 always-on; 556 }; 557 si5341_7: out@7 { 558 /* refclk7 PL CLK74 */ 559 reg = <7>; 560 always-on; 561 }; 562 si5341_9: out@9 { 563 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 564 reg = <9>; 565 always-on; 566 }; 567 }; 568 }; 569 i2c@2 { 570 #address-cells = <1>; 571 #size-cells = <0>; 572 reg = <2>; 573 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 574 #clock-cells = <0>; 575 compatible = "silabs,si570"; 576 reg = <0x5d>; 577 temperature-stability = <50>; 578 factory-fout = <300000000>; 579 clock-frequency = <300000000>; 580 clock-output-names = "si570_user"; 581 }; 582 }; 583 i2c@3 { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 reg = <3>; 587 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 588 #clock-cells = <0>; 589 compatible = "silabs,si570"; 590 reg = <0x5d>; 591 temperature-stability = <50>; /* copy from zc702 */ 592 factory-fout = <156250000>; 593 clock-frequency = <148500000>; 594 clock-output-names = "si570_mgt"; 595 }; 596 }; 597 i2c@4 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 reg = <4>; 601 /* SI5328 - u20 */ 602 }; 603 /* 5 - 7 unconnected */ 604 }; 605 606 i2c-mux@75 { 607 compatible = "nxp,pca9548"; /* u135 */ 608 #address-cells = <1>; 609 #size-cells = <0>; 610 reg = <0x75>; 611 612 i2c@0 { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 reg = <0>; 616 /* HPC0_IIC */ 617 }; 618 i2c@1 { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 reg = <1>; 622 /* HPC1_IIC */ 623 }; 624 i2c@2 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 reg = <2>; 628 /* SYSMON */ 629 }; 630 i2c@3 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <3>; 634 /* DDR4 SODIMM */ 635 }; 636 i2c@4 { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 reg = <4>; 640 /* SEP 3 */ 641 }; 642 i2c@5 { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 reg = <5>; 646 /* SEP 2 */ 647 }; 648 i2c@6 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 reg = <6>; 652 /* SEP 1 */ 653 }; 654 i2c@7 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 reg = <7>; 658 /* SEP 0 */ 659 }; 660 }; 661}; 662 663&pinctrl0 { 664 status = "okay"; 665 pinctrl_i2c0_default: i2c0-default { 666 mux { 667 groups = "i2c0_3_grp"; 668 function = "i2c0"; 669 }; 670 671 conf { 672 groups = "i2c0_3_grp"; 673 bias-pull-up; 674 slew-rate = <SLEW_RATE_SLOW>; 675 power-source = <IO_STANDARD_LVCMOS18>; 676 }; 677 }; 678 679 pinctrl_i2c0_gpio: i2c0-gpio { 680 mux { 681 groups = "gpio0_14_grp", "gpio0_15_grp"; 682 function = "gpio0"; 683 }; 684 685 conf { 686 groups = "gpio0_14_grp", "gpio0_15_grp"; 687 slew-rate = <SLEW_RATE_SLOW>; 688 power-source = <IO_STANDARD_LVCMOS18>; 689 }; 690 }; 691 692 pinctrl_i2c1_default: i2c1-default { 693 mux { 694 groups = "i2c1_4_grp"; 695 function = "i2c1"; 696 }; 697 698 conf { 699 groups = "i2c1_4_grp"; 700 bias-pull-up; 701 slew-rate = <SLEW_RATE_SLOW>; 702 power-source = <IO_STANDARD_LVCMOS18>; 703 }; 704 }; 705 706 pinctrl_i2c1_gpio: i2c1-gpio { 707 mux { 708 groups = "gpio0_16_grp", "gpio0_17_grp"; 709 function = "gpio0"; 710 }; 711 712 conf { 713 groups = "gpio0_16_grp", "gpio0_17_grp"; 714 slew-rate = <SLEW_RATE_SLOW>; 715 power-source = <IO_STANDARD_LVCMOS18>; 716 }; 717 }; 718 719 pinctrl_uart0_default: uart0-default { 720 mux { 721 groups = "uart0_4_grp"; 722 function = "uart0"; 723 }; 724 725 conf { 726 groups = "uart0_4_grp"; 727 slew-rate = <SLEW_RATE_SLOW>; 728 power-source = <IO_STANDARD_LVCMOS18>; 729 }; 730 731 conf-rx { 732 pins = "MIO18"; 733 bias-high-impedance; 734 }; 735 736 conf-tx { 737 pins = "MIO19"; 738 bias-disable; 739 }; 740 }; 741 742 pinctrl_uart1_default: uart1-default { 743 mux { 744 groups = "uart1_5_grp"; 745 function = "uart1"; 746 }; 747 748 conf { 749 groups = "uart1_5_grp"; 750 slew-rate = <SLEW_RATE_SLOW>; 751 power-source = <IO_STANDARD_LVCMOS18>; 752 }; 753 754 conf-rx { 755 pins = "MIO21"; 756 bias-high-impedance; 757 }; 758 759 conf-tx { 760 pins = "MIO20"; 761 bias-disable; 762 }; 763 }; 764 765 pinctrl_usb0_default: usb0-default { 766 mux { 767 groups = "usb0_0_grp"; 768 function = "usb0"; 769 }; 770 771 conf { 772 groups = "usb0_0_grp"; 773 slew-rate = <SLEW_RATE_SLOW>; 774 power-source = <IO_STANDARD_LVCMOS18>; 775 }; 776 777 conf-rx { 778 pins = "MIO52", "MIO53", "MIO55"; 779 bias-high-impedance; 780 }; 781 782 conf-tx { 783 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 784 "MIO60", "MIO61", "MIO62", "MIO63"; 785 bias-disable; 786 }; 787 }; 788 789 pinctrl_gem3_default: gem3-default { 790 mux { 791 function = "ethernet3"; 792 groups = "ethernet3_0_grp"; 793 }; 794 795 conf { 796 groups = "ethernet3_0_grp"; 797 slew-rate = <SLEW_RATE_SLOW>; 798 power-source = <IO_STANDARD_LVCMOS18>; 799 }; 800 801 conf-rx { 802 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 803 "MIO75"; 804 bias-high-impedance; 805 low-power-disable; 806 }; 807 808 conf-tx { 809 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 810 "MIO69"; 811 bias-disable; 812 low-power-enable; 813 }; 814 815 mux-mdio { 816 function = "mdio3"; 817 groups = "mdio3_0_grp"; 818 }; 819 820 conf-mdio { 821 groups = "mdio3_0_grp"; 822 slew-rate = <SLEW_RATE_SLOW>; 823 power-source = <IO_STANDARD_LVCMOS18>; 824 bias-disable; 825 }; 826 }; 827 828 pinctrl_can1_default: can1-default { 829 mux { 830 function = "can1"; 831 groups = "can1_6_grp"; 832 }; 833 834 conf { 835 groups = "can1_6_grp"; 836 slew-rate = <SLEW_RATE_SLOW>; 837 power-source = <IO_STANDARD_LVCMOS18>; 838 }; 839 840 conf-rx { 841 pins = "MIO25"; 842 bias-high-impedance; 843 }; 844 845 conf-tx { 846 pins = "MIO24"; 847 bias-disable; 848 }; 849 }; 850 851 pinctrl_sdhci1_default: sdhci1-default { 852 mux { 853 groups = "sdio1_0_grp"; 854 function = "sdio1"; 855 }; 856 857 conf { 858 groups = "sdio1_0_grp"; 859 slew-rate = <SLEW_RATE_SLOW>; 860 power-source = <IO_STANDARD_LVCMOS18>; 861 bias-disable; 862 }; 863 864 mux-cd { 865 groups = "sdio1_cd_0_grp"; 866 function = "sdio1_cd"; 867 }; 868 869 conf-cd { 870 groups = "sdio1_cd_0_grp"; 871 bias-high-impedance; 872 bias-pull-up; 873 slew-rate = <SLEW_RATE_SLOW>; 874 power-source = <IO_STANDARD_LVCMOS18>; 875 }; 876 877 mux-wp { 878 groups = "sdio1_wp_0_grp"; 879 function = "sdio1_wp"; 880 }; 881 882 conf-wp { 883 groups = "sdio1_wp_0_grp"; 884 bias-high-impedance; 885 bias-pull-up; 886 slew-rate = <SLEW_RATE_SLOW>; 887 power-source = <IO_STANDARD_LVCMOS18>; 888 }; 889 }; 890 891 pinctrl_gpio_default: gpio-default { 892 mux-sw { 893 function = "gpio0"; 894 groups = "gpio0_22_grp", "gpio0_23_grp"; 895 }; 896 897 conf-sw { 898 groups = "gpio0_22_grp", "gpio0_23_grp"; 899 slew-rate = <SLEW_RATE_SLOW>; 900 power-source = <IO_STANDARD_LVCMOS18>; 901 }; 902 903 mux-msp { 904 function = "gpio0"; 905 groups = "gpio0_13_grp", "gpio0_38_grp"; 906 }; 907 908 conf-msp { 909 groups = "gpio0_13_grp", "gpio0_38_grp"; 910 slew-rate = <SLEW_RATE_SLOW>; 911 power-source = <IO_STANDARD_LVCMOS18>; 912 }; 913 914 conf-pull-up { 915 pins = "MIO22", "MIO23"; 916 bias-pull-up; 917 }; 918 919 conf-pull-none { 920 pins = "MIO13", "MIO38"; 921 bias-disable; 922 }; 923 }; 924}; 925 926&pcie { 927 status = "okay"; 928}; 929 930&psgtr { 931 status = "okay"; 932 /* pcie, sata, usb3, dp */ 933 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 934 clock-names = "ref0", "ref1", "ref2", "ref3"; 935}; 936 937&rtc { 938 status = "okay"; 939}; 940 941&sata { 942 status = "okay"; 943 /* SATA OOB timing settings */ 944 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 945 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 946 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 947 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 948 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 949 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 950 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 951 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 952 phy-names = "sata-phy"; 953 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 954}; 955 956/* SD1 with level shifter */ 957&sdhci1 { 958 status = "okay"; 959 no-1-8-v; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&pinctrl_sdhci1_default>; 962 xlnx,mio-bank = <1>; 963}; 964 965&uart0 { 966 status = "okay"; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&pinctrl_uart0_default>; 969}; 970 971&uart1 { 972 status = "okay"; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&pinctrl_uart1_default>; 975}; 976 977/* ULPI SMSC USB3320 */ 978&usb0 { 979 status = "okay"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&pinctrl_usb0_default>; 982 dr_mode = "host"; 983 phy-names = "usb3-phy"; 984 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 985 maximum-speed = "super-speed"; 986}; 987 988&watchdog0 { 989 status = "okay"; 990}; 991 992&zynqmp_dpdma { 993 status = "okay"; 994}; 995 996&zynqmp_dpsub { 997 status = "okay"; 998 phy-names = "dp-phy0"; 999 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 1000}; 1001