1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU102 RevA 4 * 5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU102 RevA"; 21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 nvmem0 = &eeprom; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 spi0 = &qspi; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 autorepeat; 49 sw19 { 50 label = "sw19"; 51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 52 linux,code = <KEY_DOWN>; 53 wakeup-source; 54 autorepeat; 55 }; 56 }; 57 58 leds { 59 compatible = "gpio-leds"; 60 heartbeat-led { 61 label = "heartbeat"; 62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "heartbeat"; 64 }; 65 }; 66 67 ina226-u76 { 68 compatible = "iio-hwmon"; 69 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 70 }; 71 ina226-u77 { 72 compatible = "iio-hwmon"; 73 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 74 }; 75 ina226-u78 { 76 compatible = "iio-hwmon"; 77 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 78 }; 79 ina226-u87 { 80 compatible = "iio-hwmon"; 81 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 82 }; 83 ina226-u85 { 84 compatible = "iio-hwmon"; 85 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 86 }; 87 ina226-u86 { 88 compatible = "iio-hwmon"; 89 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 90 }; 91 ina226-u93 { 92 compatible = "iio-hwmon"; 93 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 94 }; 95 ina226-u88 { 96 compatible = "iio-hwmon"; 97 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 98 }; 99 ina226-u15 { 100 compatible = "iio-hwmon"; 101 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 102 }; 103 ina226-u92 { 104 compatible = "iio-hwmon"; 105 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 106 }; 107 ina226-u79 { 108 compatible = "iio-hwmon"; 109 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 110 }; 111 ina226-u81 { 112 compatible = "iio-hwmon"; 113 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 114 }; 115 ina226-u80 { 116 compatible = "iio-hwmon"; 117 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 118 }; 119 ina226-u84 { 120 compatible = "iio-hwmon"; 121 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 122 }; 123 ina226-u16 { 124 compatible = "iio-hwmon"; 125 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 126 }; 127 ina226-u65 { 128 compatible = "iio-hwmon"; 129 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 130 }; 131 ina226-u74 { 132 compatible = "iio-hwmon"; 133 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 134 }; 135 ina226-u75 { 136 compatible = "iio-hwmon"; 137 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 138 }; 139 140 /* 48MHz reference crystal */ 141 ref48: ref48M { 142 compatible = "fixed-clock"; 143 #clock-cells = <0>; 144 clock-frequency = <48000000>; 145 }; 146 147 refhdmi: refhdmi { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <114285000>; 151 }; 152}; 153 154&can1 { 155 status = "okay"; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_can1_default>; 158}; 159 160&dcc { 161 status = "okay"; 162}; 163 164&fpd_dma_chan1 { 165 status = "okay"; 166}; 167 168&fpd_dma_chan2 { 169 status = "okay"; 170}; 171 172&fpd_dma_chan3 { 173 status = "okay"; 174}; 175 176&fpd_dma_chan4 { 177 status = "okay"; 178}; 179 180&fpd_dma_chan5 { 181 status = "okay"; 182}; 183 184&fpd_dma_chan6 { 185 status = "okay"; 186}; 187 188&fpd_dma_chan7 { 189 status = "okay"; 190}; 191 192&fpd_dma_chan8 { 193 status = "okay"; 194}; 195 196&gem3 { 197 status = "okay"; 198 phy-handle = <&phy0>; 199 phy-mode = "rgmii-id"; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_gem3_default>; 202 phy0: ethernet-phy@21 { 203 reg = <21>; 204 ti,rx-internal-delay = <0x8>; 205 ti,tx-internal-delay = <0xa>; 206 ti,fifo-depth = <0x1>; 207 ti,dp83867-rxctrl-strap-quirk; 208 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ 209 }; 210}; 211 212&gpio { 213 status = "okay"; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_gpio_default>; 216}; 217 218&i2c0 { 219 status = "okay"; 220 clock-frequency = <400000>; 221 pinctrl-names = "default", "gpio"; 222 pinctrl-0 = <&pinctrl_i2c0_default>; 223 pinctrl-1 = <&pinctrl_i2c0_gpio>; 224 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 225 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 226 227 tca6416_u97: gpio@20 { 228 compatible = "ti,tca6416"; 229 reg = <0x20>; 230 gpio-controller; /* IRQ not connected */ 231 #gpio-cells = <2>; 232 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", 233 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", 234 "", "", "", "", "", "", "", "", ""; 235 gtr-sel0-hog { 236 gpio-hog; 237 gpios = <0 0>; 238 output-low; /* PCIE = 0, DP = 1 */ 239 line-name = "sel0"; 240 }; 241 gtr-sel1-hog { 242 gpio-hog; 243 gpios = <1 0>; 244 output-high; /* PCIE = 0, DP = 1 */ 245 line-name = "sel1"; 246 }; 247 gtr-sel2-hog { 248 gpio-hog; 249 gpios = <2 0>; 250 output-high; /* PCIE = 0, USB0 = 1 */ 251 line-name = "sel2"; 252 }; 253 gtr-sel3-hog { 254 gpio-hog; 255 gpios = <3 0>; 256 output-high; /* PCIE = 0, SATA = 1 */ 257 line-name = "sel3"; 258 }; 259 }; 260 261 tca6416_u61: gpio@21 { 262 compatible = "ti,tca6416"; 263 reg = <0x21>; 264 gpio-controller; /* IRQ not connected */ 265 #gpio-cells = <2>; 266 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", 267 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", 268 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", 269 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; 270 }; 271 272 i2c-mux@75 { /* u60 */ 273 compatible = "nxp,pca9544"; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 reg = <0x75>; 277 i2c@0 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0>; 281 /* PS_PMBUS */ 282 u76: ina226@40 { /* u76 */ 283 compatible = "ti,ina226"; 284 #io-channel-cells = <1>; 285 label = "ina226-u76"; 286 reg = <0x40>; 287 shunt-resistor = <5000>; 288 }; 289 u77: ina226@41 { /* u77 */ 290 compatible = "ti,ina226"; 291 #io-channel-cells = <1>; 292 label = "ina226-u77"; 293 reg = <0x41>; 294 shunt-resistor = <5000>; 295 }; 296 u78: ina226@42 { /* u78 */ 297 compatible = "ti,ina226"; 298 #io-channel-cells = <1>; 299 label = "ina226-u78"; 300 reg = <0x42>; 301 shunt-resistor = <5000>; 302 }; 303 u87: ina226@43 { /* u87 */ 304 compatible = "ti,ina226"; 305 #io-channel-cells = <1>; 306 label = "ina226-u87"; 307 reg = <0x43>; 308 shunt-resistor = <5000>; 309 }; 310 u85: ina226@44 { /* u85 */ 311 compatible = "ti,ina226"; 312 #io-channel-cells = <1>; 313 label = "ina226-u85"; 314 reg = <0x44>; 315 shunt-resistor = <5000>; 316 }; 317 u86: ina226@45 { /* u86 */ 318 compatible = "ti,ina226"; 319 #io-channel-cells = <1>; 320 label = "ina226-u86"; 321 reg = <0x45>; 322 shunt-resistor = <5000>; 323 }; 324 u93: ina226@46 { /* u93 */ 325 compatible = "ti,ina226"; 326 #io-channel-cells = <1>; 327 label = "ina226-u93"; 328 reg = <0x46>; 329 shunt-resistor = <5000>; 330 }; 331 u88: ina226@47 { /* u88 */ 332 compatible = "ti,ina226"; 333 #io-channel-cells = <1>; 334 label = "ina226-u88"; 335 reg = <0x47>; 336 shunt-resistor = <5000>; 337 }; 338 u15: ina226@4a { /* u15 */ 339 compatible = "ti,ina226"; 340 #io-channel-cells = <1>; 341 label = "ina226-u15"; 342 reg = <0x4a>; 343 shunt-resistor = <5000>; 344 }; 345 u92: ina226@4b { /* u92 */ 346 compatible = "ti,ina226"; 347 #io-channel-cells = <1>; 348 label = "ina226-u92"; 349 reg = <0x4b>; 350 shunt-resistor = <5000>; 351 }; 352 }; 353 i2c@1 { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 reg = <1>; 357 /* PL_PMBUS */ 358 u79: ina226@40 { /* u79 */ 359 compatible = "ti,ina226"; 360 #io-channel-cells = <1>; 361 label = "ina226-u79"; 362 reg = <0x40>; 363 shunt-resistor = <2000>; 364 }; 365 u81: ina226@41 { /* u81 */ 366 compatible = "ti,ina226"; 367 #io-channel-cells = <1>; 368 label = "ina226-u81"; 369 reg = <0x41>; 370 shunt-resistor = <5000>; 371 }; 372 u80: ina226@42 { /* u80 */ 373 compatible = "ti,ina226"; 374 #io-channel-cells = <1>; 375 label = "ina226-u80"; 376 reg = <0x42>; 377 shunt-resistor = <5000>; 378 }; 379 u84: ina226@43 { /* u84 */ 380 compatible = "ti,ina226"; 381 #io-channel-cells = <1>; 382 label = "ina226-u84"; 383 reg = <0x43>; 384 shunt-resistor = <5000>; 385 }; 386 u16: ina226@44 { /* u16 */ 387 compatible = "ti,ina226"; 388 #io-channel-cells = <1>; 389 label = "ina226-u16"; 390 reg = <0x44>; 391 shunt-resistor = <5000>; 392 }; 393 u65: ina226@45 { /* u65 */ 394 compatible = "ti,ina226"; 395 #io-channel-cells = <1>; 396 label = "ina226-u65"; 397 reg = <0x45>; 398 shunt-resistor = <5000>; 399 }; 400 u74: ina226@46 { /* u74 */ 401 compatible = "ti,ina226"; 402 #io-channel-cells = <1>; 403 label = "ina226-u74"; 404 reg = <0x46>; 405 shunt-resistor = <5000>; 406 }; 407 u75: ina226@47 { /* u75 */ 408 compatible = "ti,ina226"; 409 #io-channel-cells = <1>; 410 label = "ina226-u75"; 411 reg = <0x47>; 412 shunt-resistor = <5000>; 413 }; 414 }; 415 i2c@2 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 reg = <2>; 419 /* MAXIM_PMBUS - 00 */ 420 max15301@a { /* u46 */ 421 compatible = "maxim,max15301"; 422 reg = <0xa>; 423 }; 424 max15303@b { /* u4 */ 425 compatible = "maxim,max15303"; 426 reg = <0xb>; 427 }; 428 max15303@10 { /* u13 */ 429 compatible = "maxim,max15303"; 430 reg = <0x10>; 431 }; 432 max15301@13 { /* u47 */ 433 compatible = "maxim,max15301"; 434 reg = <0x13>; 435 }; 436 max15303@14 { /* u7 */ 437 compatible = "maxim,max15303"; 438 reg = <0x14>; 439 }; 440 max15303@15 { /* u6 */ 441 compatible = "maxim,max15303"; 442 reg = <0x15>; 443 }; 444 max15303@16 { /* u10 */ 445 compatible = "maxim,max15303"; 446 reg = <0x16>; 447 }; 448 max15303@17 { /* u9 */ 449 compatible = "maxim,max15303"; 450 reg = <0x17>; 451 }; 452 max15301@18 { /* u63 */ 453 compatible = "maxim,max15301"; 454 reg = <0x18>; 455 }; 456 max15303@1a { /* u49 */ 457 compatible = "maxim,max15303"; 458 reg = <0x1a>; 459 }; 460 max15303@1d { /* u18 */ 461 compatible = "maxim,max15303"; 462 reg = <0x1d>; 463 }; 464 max15303@20 { /* u8 */ 465 compatible = "maxim,max15303"; 466 status = "disabled"; /* unreachable */ 467 reg = <0x20>; 468 }; 469 max20751@72 { /* u95 */ 470 compatible = "maxim,max20751"; 471 reg = <0x72>; 472 }; 473 max20751@73 { /* u96 */ 474 compatible = "maxim,max20751"; 475 reg = <0x73>; 476 }; 477 }; 478 /* Bus 3 is not connected */ 479 }; 480}; 481 482&i2c1 { 483 status = "okay"; 484 clock-frequency = <400000>; 485 pinctrl-names = "default", "gpio"; 486 pinctrl-0 = <&pinctrl_i2c1_default>; 487 pinctrl-1 = <&pinctrl_i2c1_gpio>; 488 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 489 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 490 491 /* PL i2c via PCA9306 - u45 */ 492 i2c-mux@74 { /* u34 */ 493 compatible = "nxp,pca9548"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 reg = <0x74>; 497 i2c@0 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 reg = <0>; 501 /* 502 * IIC_EEPROM 1kB memory which uses 256B blocks 503 * where every block has different address. 504 * 0 - 256B address 0x54 505 * 256B - 512B address 0x55 506 * 512B - 768B address 0x56 507 * 768B - 1024B address 0x57 508 */ 509 eeprom: eeprom@54 { /* u23 */ 510 compatible = "atmel,24c08"; 511 reg = <0x54>; 512 }; 513 }; 514 i2c@1 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <1>; 518 si5341: clock-generator@36 { /* SI5341 - u69 */ 519 compatible = "silabs,si5341"; 520 reg = <0x36>; 521 #clock-cells = <2>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 clocks = <&ref48>; 525 clock-names = "xtal"; 526 clock-output-names = "si5341"; 527 528 si5341_0: out@0 { 529 /* refclk0 for PS-GT, used for DP */ 530 reg = <0>; 531 always-on; 532 }; 533 si5341_2: out@2 { 534 /* refclk2 for PS-GT, used for USB3 */ 535 reg = <2>; 536 always-on; 537 }; 538 si5341_3: out@3 { 539 /* refclk3 for PS-GT, used for SATA */ 540 reg = <3>; 541 always-on; 542 }; 543 si5341_4: out@4 { 544 /* refclk4 for PS-GT, used for PCIE slot */ 545 reg = <4>; 546 always-on; 547 }; 548 si5341_5: out@5 { 549 /* refclk5 for PS-GT, used for PCIE */ 550 reg = <5>; 551 always-on; 552 }; 553 si5341_6: out@6 { 554 /* refclk6 PL CLK125 */ 555 reg = <6>; 556 always-on; 557 }; 558 si5341_7: out@7 { 559 /* refclk7 PL CLK74 */ 560 reg = <7>; 561 always-on; 562 }; 563 si5341_9: out@9 { 564 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 565 reg = <9>; 566 always-on; 567 }; 568 }; 569 }; 570 i2c@2 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <2>; 574 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 575 #clock-cells = <0>; 576 compatible = "silabs,si570"; 577 reg = <0x5d>; 578 temperature-stability = <50>; 579 factory-fout = <300000000>; 580 clock-frequency = <300000000>; 581 clock-output-names = "si570_user"; 582 }; 583 }; 584 i2c@3 { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <3>; 588 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 589 #clock-cells = <0>; 590 compatible = "silabs,si570"; 591 reg = <0x5d>; 592 temperature-stability = <50>; /* copy from zc702 */ 593 factory-fout = <156250000>; 594 clock-frequency = <148500000>; 595 clock-output-names = "si570_mgt"; 596 }; 597 }; 598 i2c@4 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 reg = <4>; 602 /* SI5328 - u20 */ 603 }; 604 /* 5 - 7 unconnected */ 605 }; 606 607 i2c-mux@75 { 608 compatible = "nxp,pca9548"; /* u135 */ 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <0x75>; 612 613 i2c@0 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 reg = <0>; 617 /* HPC0_IIC */ 618 }; 619 i2c@1 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <1>; 623 /* HPC1_IIC */ 624 }; 625 i2c@2 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 reg = <2>; 629 /* SYSMON */ 630 }; 631 i2c@3 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <3>; 635 /* DDR4 SODIMM */ 636 }; 637 i2c@4 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 reg = <4>; 641 /* SEP 3 */ 642 }; 643 i2c@5 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 reg = <5>; 647 /* SEP 2 */ 648 }; 649 i2c@6 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <6>; 653 /* SEP 1 */ 654 }; 655 i2c@7 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 reg = <7>; 659 /* SEP 0 */ 660 }; 661 }; 662}; 663 664&pinctrl0 { 665 status = "okay"; 666 pinctrl_i2c0_default: i2c0-default { 667 mux { 668 groups = "i2c0_3_grp"; 669 function = "i2c0"; 670 }; 671 672 conf { 673 groups = "i2c0_3_grp"; 674 bias-pull-up; 675 slew-rate = <SLEW_RATE_SLOW>; 676 power-source = <IO_STANDARD_LVCMOS18>; 677 }; 678 }; 679 680 pinctrl_i2c0_gpio: i2c0-gpio { 681 mux { 682 groups = "gpio0_14_grp", "gpio0_15_grp"; 683 function = "gpio0"; 684 }; 685 686 conf { 687 groups = "gpio0_14_grp", "gpio0_15_grp"; 688 slew-rate = <SLEW_RATE_SLOW>; 689 power-source = <IO_STANDARD_LVCMOS18>; 690 }; 691 }; 692 693 pinctrl_i2c1_default: i2c1-default { 694 mux { 695 groups = "i2c1_4_grp"; 696 function = "i2c1"; 697 }; 698 699 conf { 700 groups = "i2c1_4_grp"; 701 bias-pull-up; 702 slew-rate = <SLEW_RATE_SLOW>; 703 power-source = <IO_STANDARD_LVCMOS18>; 704 }; 705 }; 706 707 pinctrl_i2c1_gpio: i2c1-gpio { 708 mux { 709 groups = "gpio0_16_grp", "gpio0_17_grp"; 710 function = "gpio0"; 711 }; 712 713 conf { 714 groups = "gpio0_16_grp", "gpio0_17_grp"; 715 slew-rate = <SLEW_RATE_SLOW>; 716 power-source = <IO_STANDARD_LVCMOS18>; 717 }; 718 }; 719 720 pinctrl_uart0_default: uart0-default { 721 mux { 722 groups = "uart0_4_grp"; 723 function = "uart0"; 724 }; 725 726 conf { 727 groups = "uart0_4_grp"; 728 slew-rate = <SLEW_RATE_SLOW>; 729 power-source = <IO_STANDARD_LVCMOS18>; 730 }; 731 732 conf-rx { 733 pins = "MIO18"; 734 bias-high-impedance; 735 }; 736 737 conf-tx { 738 pins = "MIO19"; 739 bias-disable; 740 }; 741 }; 742 743 pinctrl_uart1_default: uart1-default { 744 mux { 745 groups = "uart1_5_grp"; 746 function = "uart1"; 747 }; 748 749 conf { 750 groups = "uart1_5_grp"; 751 slew-rate = <SLEW_RATE_SLOW>; 752 power-source = <IO_STANDARD_LVCMOS18>; 753 }; 754 755 conf-rx { 756 pins = "MIO21"; 757 bias-high-impedance; 758 }; 759 760 conf-tx { 761 pins = "MIO20"; 762 bias-disable; 763 }; 764 }; 765 766 pinctrl_usb0_default: usb0-default { 767 mux { 768 groups = "usb0_0_grp"; 769 function = "usb0"; 770 }; 771 772 conf { 773 groups = "usb0_0_grp"; 774 slew-rate = <SLEW_RATE_SLOW>; 775 power-source = <IO_STANDARD_LVCMOS18>; 776 }; 777 778 conf-rx { 779 pins = "MIO52", "MIO53", "MIO55"; 780 bias-high-impedance; 781 }; 782 783 conf-tx { 784 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 785 "MIO60", "MIO61", "MIO62", "MIO63"; 786 bias-disable; 787 }; 788 }; 789 790 pinctrl_gem3_default: gem3-default { 791 mux { 792 function = "ethernet3"; 793 groups = "ethernet3_0_grp"; 794 }; 795 796 conf { 797 groups = "ethernet3_0_grp"; 798 slew-rate = <SLEW_RATE_SLOW>; 799 power-source = <IO_STANDARD_LVCMOS18>; 800 }; 801 802 conf-rx { 803 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 804 "MIO75"; 805 bias-high-impedance; 806 low-power-disable; 807 }; 808 809 conf-tx { 810 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 811 "MIO69"; 812 bias-disable; 813 low-power-enable; 814 }; 815 816 mux-mdio { 817 function = "mdio3"; 818 groups = "mdio3_0_grp"; 819 }; 820 821 conf-mdio { 822 groups = "mdio3_0_grp"; 823 slew-rate = <SLEW_RATE_SLOW>; 824 power-source = <IO_STANDARD_LVCMOS18>; 825 bias-disable; 826 }; 827 }; 828 829 pinctrl_can1_default: can1-default { 830 mux { 831 function = "can1"; 832 groups = "can1_6_grp"; 833 }; 834 835 conf { 836 groups = "can1_6_grp"; 837 slew-rate = <SLEW_RATE_SLOW>; 838 power-source = <IO_STANDARD_LVCMOS18>; 839 }; 840 841 conf-rx { 842 pins = "MIO25"; 843 bias-high-impedance; 844 }; 845 846 conf-tx { 847 pins = "MIO24"; 848 bias-disable; 849 }; 850 }; 851 852 pinctrl_sdhci1_default: sdhci1-default { 853 mux { 854 groups = "sdio1_0_grp"; 855 function = "sdio1"; 856 }; 857 858 conf { 859 groups = "sdio1_0_grp"; 860 slew-rate = <SLEW_RATE_SLOW>; 861 power-source = <IO_STANDARD_LVCMOS18>; 862 bias-disable; 863 }; 864 865 mux-cd { 866 groups = "sdio1_cd_0_grp"; 867 function = "sdio1_cd"; 868 }; 869 870 conf-cd { 871 groups = "sdio1_cd_0_grp"; 872 bias-high-impedance; 873 bias-pull-up; 874 slew-rate = <SLEW_RATE_SLOW>; 875 power-source = <IO_STANDARD_LVCMOS18>; 876 }; 877 878 mux-wp { 879 groups = "sdio1_wp_0_grp"; 880 function = "sdio1_wp"; 881 }; 882 883 conf-wp { 884 groups = "sdio1_wp_0_grp"; 885 bias-high-impedance; 886 bias-pull-up; 887 slew-rate = <SLEW_RATE_SLOW>; 888 power-source = <IO_STANDARD_LVCMOS18>; 889 }; 890 }; 891 892 pinctrl_gpio_default: gpio-default { 893 mux-sw { 894 function = "gpio0"; 895 groups = "gpio0_22_grp", "gpio0_23_grp"; 896 }; 897 898 conf-sw { 899 groups = "gpio0_22_grp", "gpio0_23_grp"; 900 slew-rate = <SLEW_RATE_SLOW>; 901 power-source = <IO_STANDARD_LVCMOS18>; 902 }; 903 904 mux-msp { 905 function = "gpio0"; 906 groups = "gpio0_13_grp", "gpio0_38_grp"; 907 }; 908 909 conf-msp { 910 groups = "gpio0_13_grp", "gpio0_38_grp"; 911 slew-rate = <SLEW_RATE_SLOW>; 912 power-source = <IO_STANDARD_LVCMOS18>; 913 }; 914 915 conf-pull-up { 916 pins = "MIO22", "MIO23"; 917 bias-pull-up; 918 }; 919 920 conf-pull-none { 921 pins = "MIO13", "MIO38"; 922 bias-disable; 923 }; 924 }; 925}; 926 927&pcie { 928 status = "okay"; 929}; 930 931&psgtr { 932 status = "okay"; 933 /* pcie, sata, usb3, dp */ 934 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 935 clock-names = "ref0", "ref1", "ref2", "ref3"; 936}; 937 938&qspi { 939 status = "okay"; 940 is-dual = <1>; 941 flash@0 { 942 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 943 #address-cells = <1>; 944 #size-cells = <1>; 945 reg = <0x0>; 946 spi-tx-bus-width = <1>; 947 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 948 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 949 }; 950}; 951 952&rtc { 953 status = "okay"; 954}; 955 956&sata { 957 status = "okay"; 958 /* SATA OOB timing settings */ 959 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 960 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 961 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 962 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 963 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 964 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 965 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 966 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 967 phy-names = "sata-phy"; 968 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 969}; 970 971/* SD1 with level shifter */ 972&sdhci1 { 973 status = "okay"; 974 /* 975 * 1.0 revision has level shifter and this property should be 976 * removed for supporting UHS mode 977 */ 978 no-1-8-v; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&pinctrl_sdhci1_default>; 981 xlnx,mio-bank = <1>; 982}; 983 984&uart0 { 985 status = "okay"; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&pinctrl_uart0_default>; 988}; 989 990&uart1 { 991 status = "okay"; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&pinctrl_uart1_default>; 994}; 995 996/* ULPI SMSC USB3320 */ 997&usb0 { 998 status = "okay"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&pinctrl_usb0_default>; 1001 dr_mode = "host"; 1002 phy-names = "usb3-phy"; 1003 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 1004 maximum-speed = "super-speed"; 1005}; 1006 1007&watchdog0 { 1008 status = "okay"; 1009}; 1010 1011&zynqmp_dpdma { 1012 status = "okay"; 1013}; 1014 1015&zynqmp_dpsub { 1016 status = "okay"; 1017 phy-names = "dp-phy0"; 1018 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 1019}; 1020