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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2 |
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| #
b0e4672f |
| 17-Nov-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level
[ Upstream commit 3b6345e3fcf4c93a79f396121cd0e6f98f04da13 ]
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete
a
arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level
[ Upstream commit 3b6345e3fcf4c93a79f396121cd0e6f98f04da13 ]
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete
and will not be functional unless they are extended.
As the attached SD/eMMC is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the SDHCI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231117163339.89952-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Stable-dep-of: 379c7752bbd0 ("arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC")
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3 |
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| #
91e057f6 |
| 11-Sep-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am642-evm: Add boot phase tags marking
[ Upstream commit 33830e077797ce4d7317b83a145f03bfde06ad4c ]
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml)
arm64: dts: ti: k3-am642-evm: Add boot phase tags marking
[ Upstream commit 33830e077797ce4d7317b83a145f03bfde06ad4c ]
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT.
Describe the same for AM642-evm boot devices.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230911172902.1057417-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Stable-dep-of: 379c7752bbd0 ("arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC")
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
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| #
cd9f6b32 |
| 09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level
OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux an
arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level
OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.
As the attached OSPI device is only known about at the board integration
level, these nodes should only be enabled when provided with this
information.
Disable the OSPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-8-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
show more ...
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Revision tags: v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40 |
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| #
8d08d7aa |
| 21-Jul-2023 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: Use local header for SERDES MUX idle-state values
The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for
arm64: dts: ti: Use local header for SERDES MUX idle-state values
The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for bindings.
So move these constants in a header next to DTS.
Also add J784S4 SERDES4 lane definitions which were missed earlier.
Suggested-by: Nishanth Menon <nm@ti.com>
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Suggested-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@kernel.org/
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20230721125732.122421-2-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
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Revision tags: v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35 |
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| #
a4956811 |
| 15-Jun-2023 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: Unify pin group node names for make dtbs checks
Prepare for pinctrl-single yaml binding and unify pin group node names.
Let's standardize on pin group node naming ending in -pins. A
arm64: dts: ti: Unify pin group node names for make dtbs checks
Prepare for pinctrl-single yaml binding and unify pin group node names.
Let's standardize on pin group node naming ending in -pins. As we don't
necessarily have a SoC specific compatible property for pinctrl-single.
I'd rather not add a pattern match for pins somewhere in the name for all
the users.
Trying to add matches for pins-default will be futile as on the earlier
SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so
on that would need to be matched.
And as the node is a pin group, let's prefer to use naming -pins rather
than -pin as more pins may need to be added to the pin group later on.
Signed-off-by: Tony Lindgren <tony@atomide.com>
[vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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Revision tags: v6.1.34, v6.1.33, v6.1.32 |
|
| #
6b343136 |
| 01-Jun-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Use phandle to stdout UART node
Using a phandle makes it clear which UART we are choosing without needing
to resolve through an alias first.
Especially useful for boards li
arm64: dts: ti: k3-am64: Use phandle to stdout UART node
Using a phandle makes it clear which UART we are choosing without needing
to resolve through an alias first.
Especially useful for boards like the TI J721s2-EVM where the alias is
"serial2" but it actually resolves to the 8th UART instance(main_uart8).
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
27f98f3e |
| 01-Jun-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Only set UART baud for used ports
As the binding for "current-speed" states, this should only be used
when the baud rate of an attached device cannot be detected. This is
th
arm64: dts: ti: k3-am64: Only set UART baud for used ports
As the binding for "current-speed" states, this should only be used
when the baud rate of an attached device cannot be detected. This is
the case for our attached on-board USB-to-UART converter used for
early kernel console. For all other unconnected/disabled ports this
can be configured in userspace later, DT is not the place for device
configuration, especially when there are already standard ways to
set serial baud in userspace.
Remove setting baud for all disabled serial ports and move setting
it for the couple enabled ports down into the board files.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
bb867df5 |
| 06-Jun-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandl
arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-11-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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Revision tags: v6.1.31, v6.1.30, v6.1.29 |
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| #
9227c49a |
| 13-May-2023 |
Vaishnav Achath <vaishnav.a@ti.com> |
arm64: dts: ti: k3-am642-sk/evm: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdp
arm64: dts: ti: k3-am642-sk/evm: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI
flash with sector size of 256 KiB thus the size of the smallest partition
is chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
91f983ff |
| 15-May-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a
arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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Revision tags: v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25 |
|
| #
bb3d6578 |
| 14-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliases
Drop bootargs and add aliases based on base pinout of SK as per [1] and
evm per [2].
Indices chosen attempt to maintain some level of con
arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliases
Drop bootargs and add aliases based on base pinout of SK as per [1] and
evm per [2].
Indices chosen attempt to maintain some level of consistency with
existing aliases.
While at this, drop a extra EoL. While this patch could be split, it
seems trivial to add additional cleanup steps.
[1] https://www.ti.com/lit/df/sprr432/sprr432.pdf
[2] https://www.ti.com/lit/zip/swrr171
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-11-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
aca16cef |
| 14-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDR
Hold the DDR vtt regulator active for functionality.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel
arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDR
Hold the DDR vtt regulator active for functionality.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-10-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
61ee5572 |
| 14-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am642-evm: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros
arm64: dts: ti: k3-am642-evm: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-9-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
e3e1d9ab |
| 14-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am642-evm: Describe main_uart1 pins
Describe the main_uart1 pins even though it is a reserved node for
hardware complete description. This is used by other users of device
tree to
arm64: dts: ti: k3-am642-evm: Describe main_uart1 pins
Describe the main_uart1 pins even though it is a reserved node for
hardware complete description. This is used by other users of device
tree to help configure the SoC per board requirements.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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| #
cf3b25bc |
| 14-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eeprom
Enable AT24CM01 on the base board using the corresponding compatible.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros
arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eeprom
Enable AT24CM01 on the base board using the corresponding compatible.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
show more ...
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|
Revision tags: v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3 |
|
| #
4eb7aa3b |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable GPMC and ELM nodes at the board level
The GPMC node defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless it is extended with
arm64: dts: ti: k3-am64: Enable GPMC and ELM nodes at the board level
The GPMC node defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless it is extended with pinmux information.
As the pinmux is only known at the board integration level, this node
should only be enabled when provided with this information.
Disable the GPMC node in the dtsi file. Since the ELM is made to work
with the GPMC, disable it too.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-11-afd@ti.com
show more ...
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| #
4a579887 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable MCAN nodes at the board level
MCAN nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am64: Enable MCAN nodes at the board level
MCAN nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the MCAN nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-10-afd@ti.com
show more ...
|
| #
f572888b |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable MDIO nodes at the board level
MDIO nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmu
arm64: dts: ti: k3-am64: Enable MDIO nodes at the board level
MDIO nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes (in both CPSW and ICSSG) in the dtsi files and
only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-9-afd@ti.com
show more ...
|
| #
aa62d661 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node
Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be control
arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node
Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be controlled by
the MDIO node (so if it was to be disabled for instance, the pinmux
state would reflect that).
Move the MDIO pins pinmux to the MIDO nodes.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-8-afd@ti.com
show more ...
|
| #
3e21ec28 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDe
arm64: dts: ti: k3-am64: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-7-afd@ti.com
show more ...
|
| #
dcac8eaa |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable ECAP nodes at the board level
ECAP nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am64: Enable ECAP nodes at the board level
ECAP nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information. (These and the EPWM nodes could be used to trigger internal
actions but they are not used like that currently)
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the ECAP nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-6-afd@ti.com
show more ...
|
| #
ebc0ed71 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable EPWM nodes at the board level
EPWM nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am64: Enable EPWM nodes at the board level
EPWM nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the EPWM nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-5-afd@ti.com
show more ...
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| #
79d4aa62 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable SPI nodes at the board level
SPI nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
in
arm64: dts: ti: k3-am64: Enable SPI nodes at the board level
SPI nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the SPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-4-afd@ti.com
show more ...
|
| #
b80f75d8 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable I2C nodes at the board level
I2C nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
in
arm64: dts: ti: k3-am64: Enable I2C nodes at the board level
I2C nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the I2C nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-3-afd@ti.com
show more ...
|
| #
dacf4705 |
| 17-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable UART nodes at the board level
UART nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am64: Enable UART nodes at the board level
UART nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the UART nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-2-afd@ti.com
show more ...
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